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Class Information
Number: 438/401
Name: Semiconductor device manufacturing: process > Formation of electrically isolated lateral semiconductive structure > Having substrate registration feature (e.g., alignment mark)
Description: Process wherein the process of forming electrical isolation utilizes an alignment feature formed on the semiconductive substrate or forms an alignment feature for subsequent use.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5943586 |
LED array alignment mark, method and mask for forming same, and LED array alignment method |
Aug. 24, 1999 |
| 5943591 |
Integrated circuit scribe line structures and methods for making same |
Aug. 24, 1999 |
| 5940706 |
Process for preventing misalignment in split-gate flash memory cell |
Aug. 17, 1999 |
| 5936311 |
Integrated circuit alignment marks distributed throughout a surface metal line |
Aug. 10, 1999 |
| 5933743 |
Method of improving alignment signal strength by reducing refraction index at interface of materials in semiconductors |
Aug. 3, 1999 |
| 5933744 |
Alignment method for used in chemical mechanical polishing process |
Aug. 3, 1999 |
| 5926720 |
Consistent alignment mark profiles on semiconductor wafers using PVD shadowing |
Jul. 20, 1999 |
| 5926697 |
Method of forming a moisture guard ring for integrated circuit applications |
Jul. 20, 1999 |
| 5925937 |
Semiconductor wafer, wafer alignment patterns |
Jul. 20, 1999 |
| 5923990 |
Process for positioning a mask relative to a workpiece |
Jul. 13, 1999 |
| 5913113 |
Method for fabricating a thin film transistor of a liquid crystal display device |
Jun. 15, 1999 |
| 5911108 |
Method for protecting an alignment mark on a semiconductor substrate during chemical mechanical polishing and the resulting structure |
Jun. 8, 1999 |
| 5904563 |
Method for metal alignment mark generation |
May. 18, 1999 |
| 5898227 |
Alignment targets having enhanced contrast |
Apr. 27, 1999 |
| 5895251 |
Method for forming a triple-well in a semiconductor device |
Apr. 20, 1999 |
| 5893744 |
Method of forming a zero layer mark for alignment in integrated circuit manufacturing process employing shallow trench isolation |
Apr. 13, 1999 |
| 5889335 |
Semiconductor device and method of manufacturing the same |
Mar. 30, 1999 |
| 5882980 |
Process of forming bipolar alignment mark for semiconductor |
Mar. 16, 1999 |
| 5877064 |
Method for marking a wafer |
Mar. 2, 1999 |
| 5877562 |
Photo alignment structure |
Mar. 2, 1999 |
| 5877036 |
Overlay measuring method using correlation function |
Mar. 2, 1999 |
| 5872042 |
Method for alignment mark regeneration |
Feb. 16, 1999 |
| 5869383 |
High contrast, low noise alignment mark for laser trimming of redundant memory arrays |
Feb. 9, 1999 |
| 5866447 |
Modified zero layer align method of twin well MOS fabrication |
Feb. 2, 1999 |
| 5863825 |
Alignment mark contrast enhancement |
Jan. 26, 1999 |
| 5861320 |
Position detection mark and position detection method |
Jan. 19, 1999 |
| 5859478 |
Semiconductor device including a main alignment mark having peripheral minute alignment marks |
Jan. 12, 1999 |
| 5858854 |
Method for forming high contrast alignment marks |
Jan. 12, 1999 |
| 5843831 |
Process independent alignment system |
Dec. 1, 1998 |
| 5830799 |
Method for forming embedded diffusion layers using an alignment mark |
Nov. 3, 1998 |
| 5821131 |
Method for inspecting process defects occurring in semiconductor devices |
Oct. 13, 1998 |
| 5814552 |
High step process for manufacturing alignment marks for twin-well integrated circuit devices |
Sep. 29, 1998 |
| 5798292 |
Method of forming wafer alignment patterns |
Aug. 25, 1998 |
| 5786260 |
Method of fabricating a readable alignment mark structure using enhanced chemical mechanical polishing |
Jul. 28, 1998 |
| 5759873 |
Method of manufacturing chip-size package-type semiconductor device |
Jun. 2, 1998 |
| 5741733 |
Method for the production of a three-dimensional circuit arrangement |
Apr. 21, 1998 |
| 5733801 |
Method of making a semiconductor device with alignment marks |
Mar. 31, 1998 |
| 5716889 |
Method of arranging alignment marks |
Feb. 10, 1998 |
| 5700732 |
Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns |
Dec. 23, 1997 |
| 5688710 |
Method of fabricating a twin - well CMOS device |
Nov. 18, 1997 |
| 5679588 |
Method for fabricating P-wells and N-wells having optimized field and active regions |
Oct. 21, 1997 |
| 5677208 |
Method for making FET having reduced oxidation inductive stacking fault |
Oct. 14, 1997 |
| 5668030 |
Process for making identification alphanumeric code markings for mask ROM devices |
Sep. 16, 1997 |
| 5578519 |
Method for forming align key pattern in semiconductor device |
Nov. 26, 1996 |
| 5523254 |
Method for production of SOI transistor device and SOI transistor |
Jun. 4, 1996 |
| 5500392 |
Planar process using common alignment marks for well implants |
Mar. 19, 1996 |
| 5470782 |
Method for manufacturing an integrated circuit arrangement |
Nov. 28, 1995 |
| 5460984 |
Method of manufacturing a semi conductor device having a second well formed within a first well |
Oct. 24, 1995 |
| 5436173 |
Method for forming a semiconductor on insulator device |
Jul. 25, 1995 |
| 5397734 |
Method of fabricating a semiconductor device having a triple well structure |
Mar. 14, 1995 |
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