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Class Information
Number: 438/375
Name: Semiconductor device manufacturing: process > Forming bipolar transistor by formation or alteration of semiconductive active regions > Self-aligned > Dopant implantation or diffusion > Simultaneous introduction of plural dopants > Plural doping steps > Forming partially overlapping regions
Description: Process wherein the plural doping steps are affected upon localized areas which lap over each other in part.

Patents under this class:
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Patent Number Title Of Patent Date Issued
8367512 Self-aligned implants to reduce cross-talk of imaging sensors Feb. 5, 2013
7947562 Noise reduction in semiconductor device using counter-doping May. 24, 2011
7651920 Noise reduction in semiconductor device using counter-doping Jan. 26, 2010
7550355 Low-leakage transistor and manufacturing method thereof Jun. 23, 2009
7541250 Method for forming a self-aligned twin well region with simplified processing Jun. 2, 2009
7384853 Method of performing salicide processes on MOS transistors Jun. 10, 2008
7378342 Methods for forming vias varying lateral dimensions May. 27, 2008
7112501 Method of fabrication a silicon-on-insulator device with a channel stop Sep. 26, 2006
6847061 Elimination of implant damage during manufacture of HBT Jan. 25, 2005
6808999 Method of making a bipolar transistor having a reduced base transit time Oct. 26, 2004
6764918 Structure and method of making a high performance semiconductor device having a narrow doping profile Jul. 20, 2004
RE38510 Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip May. 4, 2004
6610578 Methods of manufacturing bipolar transistors for use at radio frequencies Aug. 26, 2003
6506659 High performance bipolar transistor Jan. 14, 2003
6459140 Indium-enhanced bipolar transistor Oct. 1, 2002
6368929 Method of manufacturing a semiconductor component and semiconductor component thereof Apr. 9, 2002
6329260 Analog-to-digital converter and method of fabrication Dec. 11, 2001
6180470 FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements Jan. 30, 2001
6180442 Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method Jan. 30, 2001
6156594 Fabrication of bipolar/CMOS integrated circuits and of a capacitor Dec. 5, 2000
6043130 Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base Mar. 28, 2000
5950080 Semiconductor device and method of manufacturing the same Sep. 7, 1999
5885880 Bipolar transistor device and method for manufacturing the same Mar. 23, 1999
5856228 Manufacturing method for making bipolar device having double polysilicon structure Jan. 5, 1999
5837590 Isolated vertical PNP transistor without required buried layer Nov. 17, 1998
5726069 Use of oblique implantation in forming emitter of bipolar transistor Mar. 10, 1998
5569613 Method of making bipolar junction transistor Oct. 29, 1996
5492844 Method of manufacturing increased conductivity base contact/feeders with self-aligned structures Feb. 20, 1996
5482873 Method for fabricating a bipolar power transistor Jan. 9, 1996
5453387 Fabrication method of semiconductor device with neighboring n- and p-type regions Sep. 26, 1995
5336926 Bipolar junction exhibiting suppressed kirk effect Aug. 9, 1994
5286660 Method for doping a semiconductor wafer having a diffusivity enhancement region Feb. 15, 1994
5273934 Method for producing a doped region in a substrate Dec. 28, 1993
5183768 Method of fabricating semiconductor device by forming doped regions that limit width of the base Feb. 2, 1993
5098638 Method of manufacturing a semiconductor device Mar. 24, 1992
5096843 Method of manufacturing a bipolar CMOS device Mar. 17, 1992
5091321 Method for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuit Feb. 25, 1992
5077227 Semiconductor device and method for fabricating the same Dec. 31, 1991
5064773 Method of forming bipolar transistor having closely spaced device regions Nov. 12, 1991
5061646 Method for forming a self-aligned bipolar transistor Oct. 29, 1991
5055419 Method of manufacturing a bipolar transistor Oct. 8, 1991
5047357 Method for forming emitters in a BiCMOS process Sep. 10, 1991
5045484 Fabrication method of a BIMOS semiconductor device Sep. 3, 1991
5026654 Method of manufacturing a semiconductor device utilizing a single polycrystalline layer for all electrodes Jun. 25, 1991
5013677 Method for manufacture of semiconductor device May. 7, 1991
5013671 Process for reduced emitter-base capacitance in bipolar transistor May. 7, 1991
5010034 CMOS and bipolar fabrication process using selective epitaxial growth scalable to below 0.5 micron Apr. 23, 1991
4994400 Method of fabricating a semiconductor device using a tri-layer structure and conductive sidewalls Feb. 19, 1991
4952521 Process for fabricating a semiconductor device with selective growth of a metal silicide Aug. 28, 1990
4898837 Method of fabricating a semiconductor integrated circuit Feb. 6, 1990

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