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Class Information
Number: 438/374
Name: Semiconductor device manufacturing: process > Forming bipolar transistor by formation or alteration of semiconductive active regions > Self-aligned > Dopant implantation or diffusion > Simultaneous introduction of plural dopants > Plural doping steps > Multiple ion implantation steps > Using same conductivity-type dopant
Description: Process wherein the same conductivity-type electrically active dopant ion is introduced using plural ion implantation steps.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7550355 |
Low-leakage transistor and manufacturing method thereof |
Jun. 23, 2009 |
| 7468305 |
Forming pocket and LDD regions using separate masks |
Dec. 23, 2008 |
| 7384853 |
Method of performing salicide processes on MOS transistors |
Jun. 10, 2008 |
| 7354841 |
Method for fabricating photodiode of CMOS image sensor |
Apr. 8, 2008 |
| 7300851 |
Method of fabricating a silicon-on-insulator device with a channel stop |
Nov. 27, 2007 |
| 7288829 |
Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide |
Oct. 30, 2007 |
| 7169674 |
Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier |
Jan. 30, 2007 |
| 7112501 |
Method of fabrication a silicon-on-insulator device with a channel stop |
Sep. 26, 2006 |
| 7001856 |
Method of calculating a pressure compensation recipe for a semiconductor wafer implanter |
Feb. 21, 2006 |
| 6908810 |
Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation |
Jun. 21, 2005 |
| 6887765 |
Method for manufacturing a bipolar junction transistor |
May. 3, 2005 |
| 6777302 |
Nitride pedestal for raised extrinsic base HBT process |
Aug. 17, 2004 |
| 6727165 |
Fabrication of metal contacts for deep-submicron technologies |
Apr. 27, 2004 |
| 6716712 |
Process for producing two differently doped adjacent regions in an integrated semiconductor |
Apr. 6, 2004 |
| 6716727 |
Methods and apparatus for plasma doping and ion implantation in an integrated processing system |
Apr. 6, 2004 |
| 6459140 |
Indium-enhanced bipolar transistor |
Oct. 1, 2002 |
| 6458667 |
High power PMOS device |
Oct. 1, 2002 |
| 6436779 |
Semiconductor device having a plurality of resistive paths |
Aug. 20, 2002 |
| 6352887 |
Merged bipolar and CMOS circuit and method |
Mar. 5, 2002 |
| 6265275 |
Method of selectively doping the intrinsic collector of a vertical bipolar transistor with epitaxial base |
Jul. 24, 2001 |
| 6232182 |
Non-volatile semiconductor memory device including memory transistor with a composite gate structure and method of manufacturing the same |
May. 15, 2001 |
| 6150200 |
Semiconductor device and method of making |
Nov. 21, 2000 |
| 5966599 |
Method for fabricating a low trigger voltage silicon controlled rectifier and thick field device |
Oct. 12, 1999 |
| 5880002 |
Method for making isolated vertical PNP transistor in a digital BiCMOS process |
Mar. 9, 1999 |
| 5866446 |
Method of manufacturing bimos device |
Feb. 2, 1999 |
| 5846858 |
SOI-BiCMOS method |
Dec. 8, 1998 |
| 5726922 |
Assembly for removably connecting data storage devices |
Mar. 10, 1998 |
| 5681763 |
Method for making bipolar transistors having indium doped base |
Oct. 28, 1997 |
| 5571731 |
Procedure for the manufacture of bipolar transistors without epitaxy and with fully implanted base and collector regions which are self-positioning relative to each other |
Nov. 5, 1996 |
| 5569613 |
Method of making bipolar junction transistor |
Oct. 29, 1996 |
| 5554543 |
Process for fabricating bipolar junction transistor having reduced parasitic capacitance |
Sep. 10, 1996 |
| 5496746 |
Method for fabricating a bipolar junction transistor exhibiting improved beta and punch-through characteristics |
Mar. 5, 1996 |
| 5492844 |
Method of manufacturing increased conductivity base contact/feeders with self-aligned structures |
Feb. 20, 1996 |
| 5482873 |
Method for fabricating a bipolar power transistor |
Jan. 9, 1996 |
| 5478760 |
Process for fabricating a vertical bipolar junction transistor |
Dec. 26, 1995 |
| 5453387 |
Fabrication method of semiconductor device with neighboring n- and p-type regions |
Sep. 26, 1995 |
| 5444003 |
Method and structure for creating a self-aligned bicmos-compatible bipolar transistor with a laterally graded emitter structure |
Aug. 22, 1995 |
| 5429959 |
Process for simultaneously fabricating a bipolar transistor and a field-effect transistor |
Jul. 4, 1995 |
| 5342794 |
Method for forming laterally graded deposit-type emitter for bipolar transistor |
Aug. 30, 1994 |
| 5336926 |
Bipolar junction exhibiting suppressed kirk effect |
Aug. 9, 1994 |
| 5328859 |
Method of making high voltage PNP bipolar transistor in CMOS |
Jul. 12, 1994 |
| 5320972 |
Method of forming a bipolar transistor |
Jun. 14, 1994 |
| 5306649 |
Method for producing a fully walled emitter-base structure in a bipolar transistor |
Apr. 26, 1994 |
| 5254485 |
Method for manufacturing bipolar semiconductor device |
Oct. 19, 1993 |
| 5194926 |
Semiconductor device having an inverse-T bipolar transistor |
Mar. 16, 1993 |
| 5183768 |
Method of fabricating semiconductor device by forming doped regions that limit width of the base |
Feb. 2, 1993 |
| 5128272 |
Self-aligned planar monolithic integrated circuit vertical transistor process |
Jul. 7, 1992 |
| 5108935 |
Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities |
Apr. 28, 1992 |
| 5091336 |
Method of making a high breakdown active device structure with low series resistance |
Feb. 25, 1992 |
| 5077227 |
Semiconductor device and method for fabricating the same |
Dec. 31, 1991 |
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