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Class Information
Number: 438/363
Name: Semiconductor device manufacturing: process > Forming bipolar transistor by formation or alteration of semiconductive active regions > Including isolation structure > Recessed oxide by localized oxidation (i.e., locos) > With epitaxial semiconductor layer formation
Description: Process for making a bipolar transistor utilizing in addition to the recessed oxide the formation of an epitaxial semiconductor layer.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7378324 |
Selective links in silicon hetero-junction bipolar transistors using carbon doping and method of forming same |
May. 27, 2008 |
| 7033895 |
Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process |
Apr. 25, 2006 |
| 6881641 |
Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same |
Apr. 19, 2005 |
| 6767798 |
Method of forming self-aligned NPN transistor with raised extrinsic base |
Jul. 27, 2004 |
| 6699760 |
Method for growing layers of group III-nitride semiconductor having electrically passivated threading defects |
Mar. 2, 2004 |
| 6624045 |
Thermal conducting trench in a seminconductor structure and method for forming the same |
Sep. 23, 2003 |
| 6593200 |
Method of forming an integrated inductor and high speed interconnect in a planarized process with shallow trench isolation |
Jul. 15, 2003 |
| 6579774 |
Semiconductor device fabrication method |
Jun. 17, 2003 |
| 6503773 |
Low threading dislocation density relaxed mismatched epilayers without high temperature growth |
Jan. 7, 2003 |
| 6444591 |
Method for reducing contamination prior to epitaxial growth and related structure |
Sep. 3, 2002 |
| 6436780 |
Semiconductor device |
Aug. 20, 2002 |
| 6331470 |
Process for manufacturing a semiconductor material wafer having power regions dielectrically insulated from circuitry regions |
Dec. 18, 2001 |
| 6313000 |
Process for formation of vertically isolated bipolar transistor device |
Nov. 6, 2001 |
| 6297118 |
Vertical bipolar semiconductor power transistor with an interdigitzed geometry, with optimization of the base-to-emitter potential difference |
Oct. 2, 2001 |
| 6242313 |
Use of polysilicon field plates to improve high voltage bipolar device breakdown voltage |
Jun. 5, 2001 |
| 6228733 |
Non-selective epitaxial depostion technology |
May. 8, 2001 |
| 6171894 |
Method of manufacturing BICMOS integrated circuits on a conventional CMOS substrate |
Jan. 9, 2001 |
| 6140196 |
Method of fabricating high power bipolar junction transistor |
Oct. 31, 2000 |
| 6057184 |
Semiconductor device fabrication method using connecting implants |
May. 2, 2000 |
| 6020246 |
Forming a self-aligned epitaxial base bipolar transistor |
Feb. 1, 2000 |
| 6015726 |
Semiconductor device and method of producing the same |
Jan. 18, 2000 |
| 6010937 |
Reduction of dislocations in a heteroepitaxial semiconductor structure |
Jan. 4, 2000 |
| 5909623 |
Manufacturing method of semiconductor device |
Jun. 1, 1999 |
| 5866446 |
Method of manufacturing bimos device |
Feb. 2, 1999 |
| 5677209 |
Method for fabricating a vertical bipolar transistor |
Oct. 14, 1997 |
| 5646055 |
Method for making bipolar transistor |
Jul. 8, 1997 |
| 5643808 |
Process of manufacturing a semiconductor device |
Jul. 1, 1997 |
| 5580798 |
Method of fabricating bipolar transistor having a guard ring |
Dec. 3, 1996 |
| 5512508 |
Method and apparatus for improvement of interconnection capacitance |
Apr. 30, 1996 |
| 5500378 |
Process for forming a bipolar type semiconductor device |
Mar. 19, 1996 |
| 5416039 |
Method of making BiCDMOS structures |
May. 16, 1995 |
| 5403758 |
Process of forming a bipolar type semiconductor device |
Apr. 4, 1995 |
| 5389553 |
Methods for fabrication of transistors |
Feb. 14, 1995 |
| 5389563 |
Method of fabricating a bipolar transistor having a high ion concentration buried floating collector |
Feb. 14, 1995 |
| 5376564 |
Method of manufacturing a bipolar transistor having a decreased collector-base capacitance |
Dec. 27, 1994 |
| 5366907 |
Method of fabricating a BI-CMOS integrated circuit device |
Nov. 22, 1994 |
| 5364802 |
Method of making a semiconductor device with buried electrode |
Nov. 15, 1994 |
| 5352617 |
Method for manufacturing Bi-CMOS transistor devices |
Oct. 4, 1994 |
| 5328858 |
Method for producing the bipolar transistor |
Jul. 12, 1994 |
| 5324672 |
Manufacturing method for bipolar transistor |
Jun. 28, 1994 |
| 5294558 |
Method of making double-self-aligned bipolar transistor structure |
Mar. 15, 1994 |
| 5244832 |
Method for fabricating a poly emitter logic array and apparatus produced thereby |
Sep. 14, 1993 |
| 5242854 |
High performance semiconductor devices and their manufacture |
Sep. 7, 1993 |
| 5238850 |
Bi-MOS type semiconductor integrated circuit device having high-frequency characteristics and method of making the same |
Aug. 24, 1993 |
| 5229307 |
Method of making extended silicide and external contact |
Jul. 20, 1993 |
| 5213988 |
Method of manufacturing bipolar transistor with self-aligned base regions |
May. 25, 1993 |
| 5208169 |
Method of forming high voltage bipolar transistor for a BICMOS integrated circuit |
May. 4, 1993 |
| 5139961 |
Reducing base resistance of a BJT by forming a self aligned silicide in the single crystal region of the extrinsic base |
Aug. 18, 1992 |
| 5137839 |
Method of manufacturing a bipolar transistor having polysilicon layer which serves as an emitter electrode and passivating dangling bonds |
Aug. 11, 1992 |
| 5098638 |
Method of manufacturing a semiconductor device |
Mar. 24, 1992 |
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