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Class Information
Number: 438/357
Name: Semiconductor device manufacturing: process > Forming bipolar transistor by formation or alteration of semiconductive active regions > Including isolation structure > Isolation by pn junction only > Including epitaxial semiconductor layer formation
Description: Process for making a junction isolated bipolar transistor utilizing the formation of an epitaxial semiconductor layer.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7384802 |
ESD protection device for high voltage |
Jun. 10, 2008 |
| 7381623 |
Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance |
Jun. 3, 2008 |
| 7371650 |
Method for producing a transistor structure |
May. 13, 2008 |
| 7332408 |
Isolation trenches for memory devices |
Feb. 19, 2008 |
| 7320922 |
Integrated circuit and method for manufacturing an integrated circuit on a semiconductor chip |
Jan. 22, 2008 |
| 7273815 |
Etch features with reduced line edge roughness |
Sep. 25, 2007 |
| 7268043 |
Semiconductor device and method of manufacturing the same |
Sep. 11, 2007 |
| 7259069 |
Semiconductor device and method of manufacturing the same |
Aug. 21, 2007 |
| 7195985 |
CMOS transistor junction regions formed by a CVD etching and deposition sequence |
Mar. 27, 2007 |
| 7151035 |
Semiconductor device and manufacturing method thereof |
Dec. 19, 2006 |
| 7135364 |
Method of fabricating semiconductor integrated circuit |
Nov. 14, 2006 |
| 7118981 |
Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor |
Oct. 10, 2006 |
| 7037798 |
Bipolar transistor structure with self-aligned raised extrinsic base and methods |
May. 2, 2006 |
| 6977426 |
Semiconductor device including high speed transistors and high voltage transistors disposed on a single substrate |
Dec. 20, 2005 |
| 6939773 |
Semiconductor devices and manufacturing methods thereof |
Sep. 6, 2005 |
| 6919253 |
Method of forming a semiconductor device including simultaneously forming a single crystalline epitaxial layer and a polycrystalline or amorphous layer |
Jul. 19, 2005 |
| 6900105 |
Semiconductor device and method of manufacture |
May. 31, 2005 |
| 6893934 |
Bipolar transistor device having phosphorous |
May. 17, 2005 |
| 6881641 |
Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same |
Apr. 19, 2005 |
| 6815801 |
Vertical bipolar transistor and a method of manufacture therefor including two epitaxial layers and a buried layer |
Nov. 9, 2004 |
| 6806158 |
Mixed crystal layer growing method and device, and semiconductor device |
Oct. 19, 2004 |
| 6780725 |
METHOD FOR FORMING A SEMICONDUCTOR DEVICE INCLUDING FORMING VERTICAL NPN AND PNP TRANSISTORS BY EXPOSING THE EPITAXIAL LAYER, FORMING A MONOCRYSTAL LAYER AND ADJUSTING THE IMPURITY CONCENTRATI |
Aug. 24, 2004 |
| 6767798 |
Method of forming self-aligned NPN transistor with raised extrinsic base |
Jul. 27, 2004 |
| 6756273 |
Semiconductor component and method of manufacturing |
Jun. 29, 2004 |
| 6693344 |
Semiconductor device having low and high breakdown voltage transistors |
Feb. 17, 2004 |
| 6649482 |
Bipolar transistor with a silicon germanium base and an ultra small self-aligned polysilicon emitter and method of forming the transistor |
Nov. 18, 2003 |
| 6627515 |
Method of fabricating a non-floating body device with enhanced performance |
Sep. 30, 2003 |
| 6607960 |
Bipolar transistor manufacturing method |
Aug. 19, 2003 |
| 6593199 |
Method of manufacturing a semiconductor component and semiconductor component thereof |
Jul. 15, 2003 |
| 6579752 |
Phosphorus dopant control in low-temperature Si and SiGe epitaxy |
Jun. 17, 2003 |
| 6541345 |
Semiconductor device with SOI structure |
Apr. 1, 2003 |
| 6518139 |
Power semiconductor device structure with vertical PNP transistor |
Feb. 11, 2003 |
| 6506657 |
Process for forming damascene-type isolation structure for BJT device formed in trench |
Jan. 14, 2003 |
| 6495421 |
Manufacture of semiconductor material and devices using that material |
Dec. 17, 2002 |
| 6489212 |
Semiconductor device and method for fabricating the same |
Dec. 3, 2002 |
| 6475849 |
Method for reducing base resistance in a bipolar transistor |
Nov. 5, 2002 |
| 6426265 |
Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology |
Jul. 30, 2002 |
| 6420771 |
Trench isolated bipolar transistor structure integrated with CMOS technology |
Jul. 16, 2002 |
| 6395591 |
Selective substrate implant process for decoupling analog and digital grounds |
May. 28, 2002 |
| 6372597 |
Method and a circuit for improving the effectiveness of ESD protection in circuit structures formed in a semiconductor substrate |
Apr. 16, 2002 |
| 6335256 |
Method of manufacturing a bipolar transistor |
Jan. 1, 2002 |
| 6329260 |
Analog-to-digital converter and method of fabrication |
Dec. 11, 2001 |
| 6313000 |
Process for formation of vertically isolated bipolar transistor device |
Nov. 6, 2001 |
| 6297118 |
Vertical bipolar semiconductor power transistor with an interdigitzed geometry, with optimization of the base-to-emitter potential difference |
Oct. 2, 2001 |
| 6238991 |
Fabrication process of semiconductor device having an epitaxial substrate |
May. 29, 2001 |
| 6235601 |
Method of manufacturing a self-aligned vertical bipolar transistor |
May. 22, 2001 |
| 6225181 |
Trench isolated bipolar transistor structure integrated with CMOS technology |
May. 1, 2001 |
| 6211028 |
Twin current bipolar device with hi-lo base profile |
Apr. 3, 2001 |
| 6211029 |
Process of fabricating a bipolar transistor having lightly doped epitaxial collector region constant in dopant impurity |
Apr. 3, 2001 |
| 6184100 |
Method of manufacturing a photodiode |
Feb. 6, 2001 |
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