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Class Information
Number: 438/353
Name: Semiconductor device manufacturing: process > Forming bipolar transistor by formation or alteration of semiconductive active regions > Including isolation structure
Description: Process for making a bipolar transistor having a structure which serves to at least partially electrically isolate the semiconductive region in which the transistor is formed from laterally adjacent semiconductive regions.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7611953 |
Bipolar transistor with isolation and direct contacts |
Nov. 3, 2009 |
| 7595253 |
Method of forming the semiconductor device |
Sep. 29, 2009 |
| 7541249 |
Process for producing a base connection of a bipolar transistor |
Jun. 2, 2009 |
| 7485943 |
Dielectric isolation type semiconductor device and manufacturing method therefor |
Feb. 3, 2009 |
| 7393731 |
Semiconductor device and method of manufacturing the same |
Jul. 1, 2008 |
| 7371650 |
Method for producing a transistor structure |
May. 13, 2008 |
| 7364957 |
Method and apparatus for semiconductor device with improved source/drain junctions |
Apr. 29, 2008 |
| 7354812 |
Multiple-depth STI trenches in integrated circuit fabrication |
Apr. 8, 2008 |
| 7205631 |
Poly-silicon stringer fuse |
Apr. 17, 2007 |
| 7196394 |
Method and apparatus for a deposited fill layer |
Mar. 27, 2007 |
| 7172914 |
Method of making uniform oxide layer |
Feb. 6, 2007 |
| 7135364 |
Method of fabricating semiconductor integrated circuit |
Nov. 14, 2006 |
| 7125780 |
Dielectric isolation type semiconductor device and method for manufacturing the same |
Oct. 24, 2006 |
| 7122431 |
Methods of fabrication metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions |
Oct. 17, 2006 |
| 7049677 |
Low cost dielectric isolation method for integration of vertical power MOSFET and lateral driver devices |
May. 23, 2006 |
| 7012319 |
System for integrating a circuit on an isolation layer and method thereof |
Mar. 14, 2006 |
| 7008851 |
Silicon-germanium mesa transistor |
Mar. 7, 2006 |
| 6991982 |
Method of manufacturing a semiconductor non-volatile memory |
Jan. 31, 2006 |
| 6964907 |
Method of etching a lateral trench under an extrinsic base and improved bipolar transistor |
Nov. 15, 2005 |
| 6962842 |
Method of removing a sacrificial emitter feature in a BICMOS process with a super self-aligned BJT |
Nov. 8, 2005 |
| 6955957 |
Method of forming a floating gate in a flash memory device |
Oct. 18, 2005 |
| 6949438 |
Method of fabricating a bipolar junction transistor |
Sep. 27, 2005 |
| 6943088 |
Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding |
Sep. 13, 2005 |
| 6927112 |
Radical processing of a sub-nanometer insulation film |
Aug. 9, 2005 |
| 6908821 |
Apparatus for adjusting input capacitance of semiconductor device and fabricating method |
Jun. 21, 2005 |
| 6909163 |
High-frequency oscillator for an integrated semiconductor circuit and the use thereof |
Jun. 21, 2005 |
| 6902975 |
Non-volatile memory technology compatible with 1T-RAM process |
Jun. 7, 2005 |
| 6902971 |
Transistor sidewall spacer stress modulation |
Jun. 7, 2005 |
| 6900105 |
Semiconductor device and method of manufacture |
May. 31, 2005 |
| 6876054 |
Integrable DC/AC voltage transformer/isolator and ultra-large-scale circuit incorporating the same |
Apr. 5, 2005 |
| 6872447 |
Surface-protective pressure-sensitive adhesive sheet |
Mar. 29, 2005 |
| 6830988 |
Method of forming an isolation structure for an integrated circuit utilizing grown and deposited oxide |
Dec. 14, 2004 |
| 6830977 |
METHODS OF FORMING AN ISOLATION TRENCH IN A SEMICONDUCTOR, METHODS OF FORMING AN ISOLATION TRENCH IN A SURFACE OF A SILICON WAFER, METHODS OF FORMING AN ISOLATION TRENCH-ISOLATED TRANSISTOR, T |
Dec. 14, 2004 |
| 6822325 |
Isolating temperature sensitive components from heat sources in integrated circuits |
Nov. 23, 2004 |
| 6815801 |
Vertical bipolar transistor and a method of manufacture therefor including two epitaxial layers and a buried layer |
Nov. 9, 2004 |
| 6803259 |
Silicon controlled rectifier for sige process, manufacturing method thereof and integrated circuit including the same |
Oct. 12, 2004 |
| 6797579 |
Semiconductor device having trench isolation structure and method of fabricating the same |
Sep. 28, 2004 |
| 6764922 |
Method of formation of an oxynitride shallow trench isolation |
Jul. 20, 2004 |
| 6759303 |
Complementary vertical bipolar junction transistors fabricated of silicon-on-sapphire utilizing wide base PNP transistors |
Jul. 6, 2004 |
| 6734524 |
Electronic component and method of manufacturing same |
May. 11, 2004 |
| 6656812 |
Vertical bipolar transistor having little low-frequency noise and high current gain, and corresponding fabrication process |
Dec. 2, 2003 |
| 6639296 |
Semiconductor device and method of manufacturing the same |
Oct. 28, 2003 |
| 6635543 |
SOI hybrid structure with selective epitaxial growth of silicon |
Oct. 21, 2003 |
| 6633073 |
Method and apparatus for isolating circuits using deep substrate n-well |
Oct. 14, 2003 |
| 6627515 |
Method of fabricating a non-floating body device with enhanced performance |
Sep. 30, 2003 |
| 6620654 |
Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure |
Sep. 16, 2003 |
| 6617663 |
Methods of manufacturing semiconductor devices |
Sep. 9, 2003 |
| 6586818 |
Self-aligned silicon germanium heterojunction bipolar transistor device with electrostatic discharge crevice cover for salicide displacement |
Jul. 1, 2003 |
| 6570239 |
Semiconductor device having resistive element |
May. 27, 2003 |
| 6551874 |
Self-aligned STI process using nitride hard mask |
Apr. 22, 2003 |
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