| |
 |
|
Class Information
Number: 438/324
Name: Semiconductor device manufacturing: process > Forming bipolar transistor by formation or alteration of semiconductive active regions > Complementary bipolar transistors > Having common active region (i.e., integrated injection logic (i2l), etc.) > Including additional electrical device
Description: Process for making complementary bipolar transistors with shared common region having combined therewith an additional electrical device.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7271070 |
Method for producing transistors |
Sep. 18, 2007 |
| 6951790 |
Method of forming select lines for NAND memory devices |
Oct. 4, 2005 |
| 6815302 |
Method of making a bipolar transistor with an oxygen implanted emitter window |
Nov. 9, 2004 |
| 6440811 |
Method of fabricating a poly-poly capacitor with a SiGe BiCMOS integration scheme |
Aug. 27, 2002 |
| 6323097 |
Electrical overlay/spacing monitor method using a ladder resistor |
Nov. 27, 2001 |
| 6303419 |
Method for fabricating a BiCMOS device featuring twin wells and an N type epitaxial layer |
Oct. 16, 2001 |
| 6294431 |
Process of manufacture of a non-volatile memory with electric continuity of the common source lines |
Sep. 25, 2001 |
| 6232193 |
Method of forming isolated integrated injection logic gate |
May. 15, 2001 |
| 6225179 |
Semiconductor integrated bi-MOS circuit having isolating regions different in thickness between bipolar area and MOS area and process of fabrication thereof |
May. 1, 2001 |
| 6162695 |
Field ring to improve the breakdown voltage for a high voltage bipolar device |
Dec. 19, 2000 |
| 6022778 |
Process for the manufacturing of integrated circuits comprising low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells |
Feb. 8, 2000 |
| 5915186 |
Method of manufacturing heterojunction bipolar device having Si.sub.1-x Ge.sub.x base |
Jun. 22, 1999 |
| 5869381 |
RF power transistor having improved stability and gain |
Feb. 9, 1999 |
| 5770490 |
Method for producing dual work function CMOS device |
Jun. 23, 1998 |
| 5755979 |
Application of semiconductor IC fabrication techniques to the manufacturing of a conditioning head for pad conditioning during chemical-mechanical polish |
May. 26, 1998 |
| 5661066 |
Semiconductor integrated circuit |
Aug. 26, 1997 |
| 5591656 |
Semiconductor integrated circuit device with self-aligned superhigh speed bipolar transistor |
Jan. 7, 1997 |
| 5166094 |
Method of fabricating a base-coupled transistor logic |
Nov. 24, 1992 |
| 5162252 |
Method of fabricating IIL and vertical complementary bipolar transistors |
Nov. 10, 1992 |
| 5100810 |
Manufacturing method of semiconductor devices |
Mar. 31, 1992 |
| 5066602 |
Method of making semiconductor IC including polar transistors |
Nov. 19, 1991 |
| 4981807 |
Process for fabricating complementary vertical transistor memory cell |
Jan. 1, 1991 |
| 4567644 |
Method of making triple diffused ISL structure |
Feb. 4, 1986 |
| 4567501 |
Resistor structure in integrated injection logic |
Jan. 28, 1986 |
| 4546539 |
I.sup.2 L Structure and fabrication process compatible with high voltage bipolar transistors |
Oct. 15, 1985 |
| 4539742 |
Semiconductor device and method for manufacturing the same |
Sep. 10, 1985 |
| 4510676 |
Method of fabricating a lateral PNP transistor |
Apr. 16, 1985 |
| 4505766 |
Method of fabricating a semiconductor device utilizing simultaneous outdiffusion and epitaxial deposition |
Mar. 19, 1985 |
| 4476623 |
Method of fabricating a bipolar dynamic memory cell |
Oct. 16, 1984 |
| 4475280 |
Method of making an integrated circuit incorporating low voltage and high voltage semiconductor devices |
Oct. 9, 1984 |
| 4458158 |
IC Including small signal and power devices |
Jul. 3, 1984 |
| 4404738 |
Method of fabricating an I.sup.2 L element and a linear transistor on one chip |
Sep. 20, 1983 |
| 4338139 |
Method of forming Schottky-I.sup.2 L devices by implantation and laser bombardment |
Jul. 6, 1982 |
| 4272307 |
Integrated circuit with I.sup.2 L and power transistors and method for making |
Jun. 9, 1981 |
| 4255209 |
Process of fabricating an improved I.sup.2 L integrated circuit utilizing diffusion and epitaxial deposition |
Mar. 10, 1981 |
| 4197147 |
Method of manufacturing an integrated circuit including an analog circuit and an I.sup.2 L circuit utilizing staged diffusion techniques |
Apr. 8, 1980 |
| 4157268 |
Localized oxidation enhancement for an integrated injection logic circuit |
Jun. 5, 1979 |
| 4101349 |
Integrated injection logic structure fabricated by outdiffusion and epitaxial deposition |
Jul. 18, 1978 |
| 4087900 |
Fabrication of semiconductor integrated circuit structure including injection logic configuration compatible with complementary bipolar transistors utilizing simultaneous formation of device r |
May. 9, 1978 |
| 4076556 |
Method for fabrication of improved bipolar injection logic circuit |
Feb. 28, 1978 |
| 4043849 |
Planar diffusion method for an I.sup.2 L circuit including a bipolar analog circuit part |
Aug. 23, 1977 |
|
|
|
