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Class Information
Number: 438/304
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Self-aligned > Source or drain doping > Utilizing gate sidewall structure > Conductive sidewall component
Description: Process wherein the gate sidewall structure is composed at least in part of a conductive component.










Patents under this class:
1 2 3 4 5 6

Patent Number Title Of Patent Date Issued
8685817 Metal gate structures for CMOS transistor devices having reduced parasitic capacitance Apr. 1, 2014
8614124 SONOS ONO stack scaling Dec. 24, 2013
8614133 Structure and method to enabling a borderless contact to source regions and drain regions of a complementary metal oxide semiconductor (CMOS) transistor Dec. 24, 2013
8518776 Methods for producing a tunnel field-effect transistor Aug. 27, 2013
8502325 Metal high-K transistor having silicon sidewalls for reduced parasitic capacitance Aug. 6, 2013
8420492 MOS transistor and method for forming the same Apr. 16, 2013
8389369 Electronic device including a doped region disposed under and having a higher dopant concentration than a channel region and a process of forming the same Mar. 5, 2013
8283233 MOS structures that exhibit lower contact resistance and methods for fabricating the same Oct. 9, 2012
8278178 Nonvolatile memory device and method of manufacturing the same Oct. 2, 2012
8247286 Semiconductor device having transistor and method of manufacturing the same Aug. 21, 2012
8241985 Semiconductor device having gate electrode with lower impurity concentration at edge portions than above channel and method of manufacturing the same Aug. 14, 2012
8216908 Extended drain transistor and method of manufacturing the same Jul. 10, 2012
8216906 Method of manufacturing integrated circuit device with well controlled surface proximity Jul. 10, 2012
8216907 Process to fabricate a metal high-K transistor having first and second silicon sidewalls for reduced parasitic capacitance Jul. 10, 2012
8148771 Semiconductor device and method to manufacture thereof Apr. 3, 2012
8012840 Semiconductor device and method of manufacturing semiconductor device Sep. 6, 2011
8003473 Bipolar transistor with silicided sub-collector Aug. 23, 2011
7980876 Lock for mobile communication equipment Jul. 19, 2011
7981749 MOS structures that exhibit lower contact resistance and methods for fabricating the same Jul. 19, 2011
7919379 Dielectric spacer removal Apr. 5, 2011
7902032 Method for forming strained channel PMOS devices and integrated circuits therefrom Mar. 8, 2011
7855135 Method to reduce parastic capacitance in a metal high dielectric constant (MHK) transistor Dec. 21, 2010
7847348 Semiconductor apparatus Dec. 7, 2010
7843007 Metal high-k transistor having silicon sidewall for reduced parasitic capacitance Nov. 30, 2010
7786538 Semiconductor device having a nickel silicide layer on a single crystal silicon layer Aug. 31, 2010
7786586 Inductor of semiconductor device and method for manufacturing the same Aug. 31, 2010
7704816 Boron derived materials deposition method Apr. 27, 2010
7704829 Method for fabricating nonvolatile memory device Apr. 27, 2010
7682917 Disposable metallic or semiconductor gate spacer Mar. 23, 2010
7618864 Nonvolatile memory device and methods of forming the same Nov. 17, 2009
7595245 Semiconductor device having a gate electrode material feature located adjacent a gate width side of its gate electrode and a method of manufacture therefor Sep. 29, 2009
7579243 Split gate memory cell method Aug. 25, 2009
7569436 Manufacturing method of semiconductor device Aug. 4, 2009
7566615 Methods of fabricating scalable two transistor memory devices Jul. 28, 2009
7547602 Semiconductor integrated circuit device and its manufacturing method Jun. 16, 2009
7544562 Method for manufacturing a capacitor electrode structure Jun. 9, 2009
7541241 Method for fabricating memory cell Jun. 2, 2009
7537988 Differential offset spacer May. 26, 2009
7521314 Method for selective removal of a layer Apr. 21, 2009
7517757 Non-volatile memory device having dual gate and method of forming the same Apr. 14, 2009
7510941 Semiconductor device and manufacturing method of the same Mar. 31, 2009
7432168 Method for fabricating semiconductor device with thin gate spacer Oct. 7, 2008
7429527 Method of manufacturing self-aligned contact openings Sep. 30, 2008
7419870 Method of manufacturing a flash memory device Sep. 2, 2008
7419879 Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same Sep. 2, 2008
7371631 Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device May. 13, 2008
7361564 Method of manufacturing high-voltage device Apr. 22, 2008
7338870 Methods of fabricating semiconductor devices Mar. 4, 2008
7335567 Gate electrodes of semiconductor devices and methods of manufacturing the same Feb. 26, 2008
7312129 Method for producing two gates controlling the same channel Dec. 25, 2007

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