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Class Information
Number: 438/304
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Self-aligned > Source or drain doping > Utilizing gate sidewall structure > Conductive sidewall component
Description: Process wherein the gate sidewall structure is composed at least in part of a conductive component.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7618864 |
Nonvolatile memory device and methods of forming the same |
Nov. 17, 2009 |
| 7595245 |
Semiconductor device having a gate electrode material feature located adjacent a gate width side of its gate electrode and a method of manufacture therefor |
Sep. 29, 2009 |
| 7579243 |
Split gate memory cell method |
Aug. 25, 2009 |
| 7569436 |
Manufacturing method of semiconductor device |
Aug. 4, 2009 |
| 7566615 |
Methods of fabricating scalable two transistor memory devices |
Jul. 28, 2009 |
| 7547602 |
Semiconductor integrated circuit device and its manufacturing method |
Jun. 16, 2009 |
| 7544562 |
Method for manufacturing a capacitor electrode structure |
Jun. 9, 2009 |
| 7541241 |
Method for fabricating memory cell |
Jun. 2, 2009 |
| 7537988 |
Differential offset spacer |
May. 26, 2009 |
| 7521314 |
Method for selective removal of a layer |
Apr. 21, 2009 |
| 7517757 |
Non-volatile memory device having dual gate and method of forming the same |
Apr. 14, 2009 |
| 7510941 |
Semiconductor device and manufacturing method of the same |
Mar. 31, 2009 |
| 7432168 |
Method for fabricating semiconductor device with thin gate spacer |
Oct. 7, 2008 |
| 7429527 |
Method of manufacturing self-aligned contact openings |
Sep. 30, 2008 |
| 7419879 |
Transistor having gate dielectric layer of partial thickness difference and method of fabricating the same |
Sep. 2, 2008 |
| 7419870 |
Method of manufacturing a flash memory device |
Sep. 2, 2008 |
| 7371631 |
Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device |
May. 13, 2008 |
| 7361564 |
Method of manufacturing high-voltage device |
Apr. 22, 2008 |
| 7338870 |
Methods of fabricating semiconductor devices |
Mar. 4, 2008 |
| 7335567 |
Gate electrodes of semiconductor devices and methods of manufacturing the same |
Feb. 26, 2008 |
| 7312129 |
Method for producing two gates controlling the same channel |
Dec. 25, 2007 |
| 7262456 |
Bit line structure and production method thereof |
Aug. 28, 2007 |
| 7259062 |
Method of making a magnetic tunnel junction device |
Aug. 21, 2007 |
| 7220649 |
Method of manufacturing semiconductor device and the semiconductor device manufactured by the method |
May. 22, 2007 |
| 7217624 |
Non-volatile memory device with conductive sidewall spacer and method for fabricating the same |
May. 15, 2007 |
| 7189623 |
Semiconductor processing method and field effect transistor |
Mar. 13, 2007 |
| 7172944 |
Method of fabricating a semiconductor device having an elevated source/drain |
Feb. 6, 2007 |
| 7169678 |
Method of forming a semiconductor device using a silicide etching mask |
Jan. 30, 2007 |
| 7169674 |
Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier |
Jan. 30, 2007 |
| 7118977 |
System and method for improved dopant profiles in CMOS transistors |
Oct. 10, 2006 |
| 7112498 |
Methods of forming silicide layer of semiconductor device |
Sep. 26, 2006 |
| 7101766 |
Methods of fabricating semiconductor device having T-shaped gate and L-shaped spacer |
Sep. 5, 2006 |
| 7098124 |
Method of forming contact hole and method of fabricating semiconductor device |
Aug. 29, 2006 |
| 7094654 |
Manufacture of electronic devices comprising thin-film transistors |
Aug. 22, 2006 |
| 7087503 |
Shallow self isolated doped implanted silicon process |
Aug. 8, 2006 |
| 7071061 |
Method for fabricating non-volatile memory |
Jul. 4, 2006 |
| 7071046 |
Method of manufacturing a MOS transistor |
Jul. 4, 2006 |
| 7064022 |
Method of forming merged FET inverter/logic gate |
Jun. 20, 2006 |
| 7045433 |
Tip architecture with SPE for buffer and deep source/drain regions |
May. 16, 2006 |
| 7033856 |
Spacer chalcogenide memory method |
Apr. 25, 2006 |
| 7015080 |
Manufacturing method of semiconductor device |
Mar. 21, 2006 |
| 6998302 |
Method of manufacturing mosfet having a fine gate width with improvement of short channel effect |
Feb. 14, 2006 |
| 6991973 |
Manufacturing method of thin film transistor |
Jan. 31, 2006 |
| 6982201 |
Structure and fabricating method with self-aligned bit line contact to word line in split gate flash |
Jan. 3, 2006 |
| 6967143 |
Semiconductor fabrication process with asymmetrical conductive spacers |
Nov. 22, 2005 |
| 6943082 |
Method for manufacturing a nonvolatile memory device |
Sep. 13, 2005 |
| 6908833 |
Shallow self isolated doped implanted silicon process |
Jun. 21, 2005 |
| 6908822 |
Semiconductor device having an insulating layer and method for forming |
Jun. 21, 2005 |
| 6897116 |
Method and structure to improve the gate coupling ratio (GCR) for manufacturing a flash memory device |
May. 24, 2005 |
| 6867103 |
Method of fabricating an ESD device on SOI |
Mar. 15, 2005 |
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