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Class Information
Number: 438/301
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Self-aligned > Source or drain doping
Description: Process having a step for the self-aligned introduction of electrically active dopant species into the semiconductor regions of the substrate to form the transistor source or drain regions or portions thereof.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6818519 |
Method of forming organic spacers and using organic spacers to form semiconductor device features |
Nov. 16, 2004 |
| 6815358 |
Electron beam lithography method for plating sub-100 nm trenches |
Nov. 9, 2004 |
| 6812106 |
Reduced dopant deactivation of source/drain extensions using laser thermal annealing |
Nov. 2, 2004 |
| 6812121 |
Process for forming a low resistivity titanium silicide layer on a silicon semiconductor substrate |
Nov. 2, 2004 |
| 6809376 |
Semiconductor integrated circuit device and manufacture method therefore |
Oct. 26, 2004 |
| 6806149 |
Sidewall processes using alkylsilane precursors for MOS transistor fabrication |
Oct. 19, 2004 |
| 6806151 |
Methods and apparatus for inducing stress in a semiconductor device |
Oct. 19, 2004 |
| 6806152 |
Retrograde doped buried layer transistor and method for producing the same |
Oct. 19, 2004 |
| 6806153 |
Method of manufacturing a field effect transistor |
Oct. 19, 2004 |
| 6806156 |
Process for fabricating a MOS transistor of short gate length and integrated circuit comprising such a transistor |
Oct. 19, 2004 |
| 6803263 |
Method of fabricating TFT with self-aligned structure |
Oct. 12, 2004 |
| 6803287 |
Method for forming a semiconductor device having contact wires of different sectional areas |
Oct. 12, 2004 |
| 6800530 |
Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors |
Oct. 5, 2004 |
| 6797555 |
Direct implantation of fluorine into the channel region of a PMOS device |
Sep. 28, 2004 |
| 6797556 |
MOS transistor structure and method of fabrication |
Sep. 28, 2004 |
| 6797574 |
Method of fabricating W/TiN gate for MOSFETS |
Sep. 28, 2004 |
| 6797602 |
Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts |
Sep. 28, 2004 |
| 6794258 |
High-performance MOS transistor of LDD structure having a gate insulating film with a nitride central portion and oxide end portions |
Sep. 21, 2004 |
| 6790734 |
Manufacturing method of semiconductor device |
Sep. 14, 2004 |
| 6790756 |
Self aligned channel implant, elevated S/D process by gate electrode damascene |
Sep. 14, 2004 |
| 6787419 |
Method of forming an embedded memory including forming three silicon or polysilicon layers |
Sep. 7, 2004 |
| 6787426 |
Method for forming word line of semiconductor device |
Sep. 7, 2004 |
| 6780713 |
Process for manufacturing a DMOS transistor |
Aug. 24, 2004 |
| 6780720 |
Method for fabricating a nitrided silicon-oxide gate dielectric |
Aug. 24, 2004 |
| 6780722 |
Field effect transistor on insulating layer and manufacturing method |
Aug. 24, 2004 |
| 6777296 |
Semiconductor device and manufacturing method thereof |
Aug. 17, 2004 |
| 6777298 |
Elevated source drain disposable spacer CMOS |
Aug. 17, 2004 |
| 6773978 |
Methods for improved metal gate fabrication |
Aug. 10, 2004 |
| 6773997 |
Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability |
Aug. 10, 2004 |
| 6774001 |
Self-aligned gate and method |
Aug. 10, 2004 |
| 6770529 |
EDMOS device having a lattice type drift region and method of manufacturing the same |
Aug. 3, 2004 |
| 6767808 |
Method for fabricating semiconductor device |
Jul. 27, 2004 |
| 6767809 |
Method of forming ultra shallow junctions |
Jul. 27, 2004 |
| 6767831 |
Method for forming cobalt salicides |
Jul. 27, 2004 |
| 6764903 |
Dual hard mask layer patterning method |
Jul. 20, 2004 |
| 6762469 |
High performance CMOS device structure with mid-gap metal gate |
Jul. 13, 2004 |
| 6759302 |
Method of generating multiple oxides by plasma nitridation on oxide |
Jul. 6, 2004 |
| 6753232 |
Method for fabricating semiconductor device |
Jun. 22, 2004 |
| 6753235 |
Method of manufacturing CMOS thin film transistor |
Jun. 22, 2004 |
| 6750106 |
Polysilicon gate doping level variation for reduced leakage current |
Jun. 15, 2004 |
| 6746944 |
Low nisi/si interface contact resistance with preamorphizing and laser thermal annealing |
Jun. 8, 2004 |
| 6743680 |
Process for manufacturing transistors having silicon/germanium channel regions |
Jun. 1, 2004 |
| 6743685 |
Semiconductor device and method for lowering miller capacitance for high-speed microprocessors |
Jun. 1, 2004 |
| 6740555 |
Semiconductor structures and manufacturing methods |
May. 25, 2004 |
| 6737308 |
Semiconductor device having LDD-type source/drain regions and fabrication method thereof |
May. 18, 2004 |
| 6737342 |
Composite spacer scheme with low overlapped parasitic capacitance |
May. 18, 2004 |
| 6737688 |
Method for manufacturing semiconductor device |
May. 18, 2004 |
| 6734071 |
Methods of forming insulative material against conductive structures |
May. 11, 2004 |
| 6734079 |
Microelectronic fabrication having sidewall passivated microelectronic capacitor structure fabricated therein |
May. 11, 2004 |
| 6734099 |
System for preventing excess silicon consumption in ultra shallow junctions |
May. 11, 2004 |
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