Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Self-aligned > Having elevated source or drain (e.g., epitaxially formed source or drain, etc.) > Patents

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Class Information
Number: 438/300
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Self-aligned > Having elevated source or drain (e.g., epitaxially formed source or drain, etc.)
Description: Process including a step of forming the source or drain active region at a position above and laterally adjacent to the channel region of the transistor.

Patents under this class:

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Patent Number	Title Of Patent	Date Issued
7618856	Method for fabricating strained-silicon CMOS transistors	Nov. 17, 2009
7615429	Methods of fabricating field effect transistors having multiple stacked channels	Nov. 10, 2009
7611938	Semiconductor device having high drive current and method of manufacture therefor	Nov. 3, 2009
7611951	Method of fabricating MOS transistor having epitaxial region	Nov. 3, 2009
7608515	Diffusion layer for stressed semiconductor devices	Oct. 27, 2009
7608868	Semiconductor device and method for manufacturing the same	Oct. 27, 2009
7608510	Alignment of trench for MOS	Oct. 27, 2009
7605407	Composite stressors with variable element atomic concentrations in MOS devices	Oct. 20, 2009
7601583	Transistor structure of memory device and method for fabricating the same	Oct. 13, 2009
7598178	Carbon precursors for use during silicon epitaxial film formation	Oct. 6, 2009
7595247	Halo-first ultra-thin SOI FET for superior short channel control	Sep. 29, 2009
7595246	Methods of manufacturing field effect transistors having elevated source/drain regions	Sep. 29, 2009
7595245	Semiconductor device having a gate electrode material feature located adjacent a gate width side of its gate electrode and a method of manufacture therefor	Sep. 29, 2009
7592619	Epitaxy layer and method of forming the same	Sep. 22, 2009
7592231	MOS transistor and fabrication thereof	Sep. 22, 2009
7592214	Method of manufacturing a semiconductor device including epitaxially growing semiconductor epitaxial layers on a surface of semiconductor substrate	Sep. 22, 2009
7591659	Method and structure for second spacer formation for strained silicon MOS transistors	Sep. 22, 2009
7586160	Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit	Sep. 8, 2009
7582535	Method of forming MOS transistor having fully silicided metal gate electrode	Sep. 1, 2009
7579249	Methods for fabricating DRAM semiconductor devices including silicon epitaxial and metal silicide layers	Aug. 25, 2009
7579248	Resolving pattern-loading issues of SiGe stressor	Aug. 25, 2009
7572706	Source/drain stressor and method therefor	Aug. 11, 2009
7572705	Semiconductor device and method of manufacturing a semiconductor device	Aug. 11, 2009
7569434	PFETs and methods of manufacturing the same	Aug. 4, 2009
7569456	MOS transistor with elevated source and drain structures and method of fabrication thereof	Aug. 4, 2009
7566609	Method of manufacturing a semiconductor structure	Jul. 28, 2009
7560352	Selective deposition	Jul. 14, 2009
7560351	Integrated circuit arrangement with low-resistance contacts and method for production thereof	Jul. 14, 2009
7560350	Method for forming strained semiconductor device and method for forming source/drain region	Jul. 14, 2009
7560379	Semiconductive device fabricated using a raised layer to silicide the gate	Jul. 14, 2009
7557006	Methods of forming field effect transistors	Jul. 7, 2009
7557396	Semiconductor device and method of manufacturing semiconductor device	Jul. 7, 2009
7553732	Integration scheme for constrained SEG growth on poly during raised S/D processing	Jun. 30, 2009
7544576	Diffusion barrier for nickel silicides in a semiconductor fabrication process	Jun. 9, 2009
7541241	Method for fabricating memory cell	Jun. 2, 2009
7534689	Stress enhanced MOS transistor and methods for its fabrication	May. 19, 2009
7524716	Fabricating method of semiconductor structure	Apr. 28, 2009
7517764	Bulk FinFET device	Apr. 14, 2009
7517765	Method for forming germanides and devices obtained thereof	Apr. 14, 2009
7517772	Selective etch for patterning a semiconductor film deposited non-selectively	Apr. 14, 2009
7517781	Method of manufacturing semiconductor device	Apr. 14, 2009
7517806	Integrated circuit having pairs of parallel complementary FinFETs	Apr. 14, 2009
7510943	Semiconductor devices and methods of manufacture thereof	Mar. 31, 2009
7504309	Pre-silicide spacer removal	Mar. 17, 2009
7498602	Protecting silicon germanium sidewall with silicon for strained silicon/silicon mosfets	Mar. 3, 2009
7498640	Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby	Mar. 3, 2009
7494877	Methods of forming semiconductor devices including Fin structures	Feb. 24, 2009
7494884	SiGe selective growth without a hard mask	Feb. 24, 2009
7491615	Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors	Feb. 17, 2009
7488660	Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structure	Feb. 10, 2009