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Class Information
Number: 438/296
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Including isolation structure > Dielectric isolation formed by grooving and refilling with dielectric material
Description: Process for making an insulated gate field effect transistor including the step of forming an isolation structure by making a recess in the semiconductor substrate and refilling the recess with an insulative material.










Patents under this class:
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Patent Number Title Of Patent Date Issued
5674775 Isolation trench with a rounded top edge using an etch buffer layer Oct. 7, 1997
5672530 Method of making MOS transistor with controlled shallow source/drain junction Sep. 30, 1997
5624866 Semiconductor device provided with trench element isolation film and method for fabricating the same Apr. 29, 1997
5614430 Anti-punchthrough ion implantation for sub-half micron channel length MOSFET devices Mar. 25, 1997
5604159 Method of making a contact structure Feb. 18, 1997
5571738 Method of making poly LDD self-aligned channel transistors Nov. 5, 1996
5561078 Method of fabrication of semiconductor device Oct. 1, 1996
5529943 Method of making buried bit line ROM with low bit line resistance Jun. 25, 1996
5506160 Method of fabricating a self-aligned trench isolation scheme for select transistors in an alternate metal virtual ground (AMG) EPROM array Apr. 9, 1996
5436190 Method for fabricating semiconductor device isolation using double oxide spacers Jul. 25, 1995
5387534 Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells Feb. 7, 1995
5380671 Method of making non-trenched buried contact for VLSI devices Jan. 10, 1995
5366911 VLSI process with global planarization Nov. 22, 1994
5342480 Method of manufacturing a semiconductor integrated circuit device Aug. 30, 1994
5340769 Method for manufacturing semiconductor device having groove-structured isolation Aug. 23, 1994
5292683 Method of isolating semiconductor devices and arrays of memory integrated circuitry Mar. 8, 1994
5254491 Method of making a semiconductor device having improved frequency response Oct. 19, 1993
5238870 Exposure process for writing a pattern on an object Aug. 24, 1993
5225358 Method of forming late isolation with polishing Jul. 6, 1993
5202286 Method of forming three-dimensional features on substrates with adjacent insulating films Apr. 13, 1993
5177028 Trench isolation method having a double polysilicon gate formed on mesas Jan. 5, 1993
5173436 Method of manufacturing an EEPROM with trench-isolated bitlines Dec. 22, 1992
5108946 Method of forming planar isolation regions Apr. 28, 1992
5093273 Method of manufacturing a semiconductor device Mar. 3, 1992
5087584 Process for fabricating a contactless floating gate memory array utilizing wordline trench vias Feb. 11, 1992
5015601 Method of manufacturing a nonvolatile semiconductor device May. 14, 1991
4981812 Process for fabricating a semiconductor read only memory Jan. 1, 1991
4973562 Method of manufacturing a semiconductor device having interconnections located both above a semiconductor region and above an isolation region adjoining it Nov. 27, 1990
4900693 Process for making polysilicon field plate with improved suppression of parasitic transistors Feb. 13, 1990
4892840 EPROM with increased floating gate/control gate coupling Jan. 9, 1990
4874717 Semiconductor circuit containing integrated bipolar and MOS transistors on a chip and method of producing same Oct. 17, 1989
4830975 Method of manufacture a primos device May. 16, 1989
4803173 Method of fabrication of semiconductor device having a planar configuration Feb. 7, 1989
4764483 Method for burying a step in a semiconductor substrate Aug. 16, 1988
4755478 Method of forming metal-strapped polysilicon gate electrode for FET device Jul. 5, 1988
4753897 Method for providing contact separation in silicided devices using false gate Jun. 28, 1988
4737828 Method for gate electrode fabrication and symmetrical and non-symmetrical self-aligned inlay transistors made therefrom Apr. 12, 1988
4727048 Process for making isolated semiconductor structure Feb. 23, 1988
4700464 Method of forming trench isolation in an integrated circuit Oct. 20, 1987
4698900 Method of making a non-volatile memory having dielectric filled trenches Oct. 13, 1987
4688314 Method of making a planar MOS device in polysilicon Aug. 25, 1987
4683637 Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing Aug. 4, 1987
4677736 Self-aligned inlay transistor with or without source and drain self-aligned metallization extensions Jul. 7, 1987
4651411 Method of manufacturing a MOS device wherein an insulating film is deposited in a field region Mar. 24, 1987
4630343 Product for making isolated semiconductor structure Dec. 23, 1986
4596071 Method of making semiconductor devices having dielectric isolation regions Jun. 24, 1986
4566940 Manufacturing process for semiconductor integrated circuits Jan. 28, 1986
4539782 Silo for loose material in powder form Sep. 10, 1985
4532696 Method of manufacturing a semiconductor device for forming a deep field region in a semiconductor substrate Aug. 6, 1985
4529456 Method of forming bifets by forming isolation regions connected by diffusion in semiconductor substrate and epitaxial layer Jul. 16, 1985

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