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Class Information
Number: 438/296
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Including isolation structure > Dielectric isolation formed by grooving and refilling with dielectric material
Description: Process for making an insulated gate field effect transistor including the step of forming an isolation structure by making a recess in the semiconductor substrate and refilling the recess with an insulative material.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 8173516 |
Method of forming shallow trench isolation structure |
May. 8, 2012 |
| 8163621 |
High performance LDMOS device having enhanced dielectric strain layer |
Apr. 24, 2012 |
| 8158488 |
Method of increasing deposition rate of silicon dioxide on a catalyst |
Apr. 17, 2012 |
| 8148784 |
Semiconductor device having first and second device isolation layers formed of different insulation materials |
Apr. 3, 2012 |
| 8133796 |
Method for fabricating shallow trench isolation structures |
Mar. 13, 2012 |
| 8133797 |
Protective layer to enable damage free gap fill |
Mar. 13, 2012 |
| 8120094 |
Shallow trench isolation with improved structure and method of forming |
Feb. 21, 2012 |
| 8114746 |
Method for forming double gate and tri-gate transistors on a bulk substrate |
Feb. 14, 2012 |
| 8114744 |
Methods for reducing gate dielectric thinning on trench isolation edges and integrated circuits therefrom |
Feb. 14, 2012 |
| 8114743 |
Integrated circuit device with a semiconductor body and method for the production of an integrated circuit device |
Feb. 14, 2012 |
| 8110455 |
Semiconductor device and a method of manufacturing the same |
Feb. 7, 2012 |
| 8110466 |
Cross OD FinFET patterning |
Feb. 7, 2012 |
| 8101512 |
Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography |
Jan. 24, 2012 |
| 8102030 |
Semiconductor device with strain |
Jan. 24, 2012 |
| 8093084 |
Semiconductor device with photonics |
Jan. 10, 2012 |
| 8088664 |
Method of manufacturing integrated deep and shallow trench isolation structures |
Jan. 3, 2012 |
| 8084355 |
Methods of forming copper-comprising conductive lines in the fabrication of integrated circuitry |
Dec. 27, 2011 |
| 8076208 |
Method for forming transistor with high breakdown voltage using pitch multiplication technique |
Dec. 13, 2011 |
| 8076203 |
Semiconductor device and method of manufacturing the same |
Dec. 13, 2011 |
| 8072035 |
Semiconductor device and method of manufacturing the same |
Dec. 6, 2011 |
| 8067293 |
Power semiconductor device and method of manufacturing the same |
Nov. 29, 2011 |
| 8067799 |
Semiconductor device having recess channel structure and method for manufacturing the same |
Nov. 29, 2011 |
| 8062953 |
Semiconductor devices with extended active regions |
Nov. 22, 2011 |
| 8053860 |
Semiconductor device and manufacturing method of the same |
Nov. 8, 2011 |
| 8053322 |
Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom |
Nov. 8, 2011 |
| 8053272 |
Semiconductor device fabrication method |
Nov. 8, 2011 |
| 8048765 |
Method for fabricating a MOS transistor with source/well heterojunction and related structure |
Nov. 1, 2011 |
| 8043918 |
Semiconductor device and its manufacturing method |
Oct. 25, 2011 |
| 8043917 |
Method for manufacturing semiconductor device |
Oct. 25, 2011 |
| 8043912 |
Manufacturing method of a semiconductor device having polycide wiring layer |
Oct. 25, 2011 |
| 8039340 |
Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming |
Oct. 18, 2011 |
| 8039359 |
Method of forming low capacitance ESD device and structure therefor |
Oct. 18, 2011 |
| 8034691 |
HDP-CVD process, filling-in process utilizing HDP-CVD, and HDP-CVD system |
Oct. 11, 2011 |
| 8030171 |
Method of forming element isolation film and nonvolatile semiconductor memory |
Oct. 4, 2011 |
| 8030173 |
Silicon nitride hardstop encapsulation layer for STI region |
Oct. 4, 2011 |
| 8017486 |
Method of fabricating low on-resistance lateral double-diffused MOS device |
Sep. 13, 2011 |
| 8012847 |
Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry |
Sep. 6, 2011 |
| 8012831 |
Method of forming isolation layer of flash memory device |
Sep. 6, 2011 |
| 8012829 |
Semiconductor device and method of manufacturing the same |
Sep. 6, 2011 |
| 8004039 |
Field effect transistor with trench-isolated drain |
Aug. 23, 2011 |
| 7994013 |
Semiconductor device and method of fabricating the semiconductor device |
Aug. 9, 2011 |
| 7994049 |
Manufacturing method of semiconductor device including filling a connecting hole with metal film |
Aug. 9, 2011 |
| 7994061 |
Mask layout and method for forming vertical channel transistor in semiconductor device using the same |
Aug. 9, 2011 |
| 7989894 |
Fusion bonding process and structure for fabricating silicon-on-insulation (SOI) semiconductor devices |
Aug. 2, 2011 |
| 7989309 |
Method of improving a shallow trench isolation gapfill process |
Aug. 2, 2011 |
| 7977196 |
Semiconductor device with increased channel area and fabrication method thereof |
Jul. 12, 2011 |
| 7977218 |
Thin oxide dummy tiling as charge protection |
Jul. 12, 2011 |
| 7977749 |
Semiconductor device with increased channel area |
Jul. 12, 2011 |
| 7968409 |
Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof |
Jun. 28, 2011 |
| 7964467 |
Method, structure and design structure for customizing history effects of soi circuits |
Jun. 21, 2011 |
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