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Class Information
Number: 438/296
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Including isolation structure > Dielectric isolation formed by grooving and refilling with dielectric material
Description: Process for making an insulated gate field effect transistor including the step of forming an isolation structure by making a recess in the semiconductor substrate and refilling the recess with an insulative material.

Patents under this class:
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Patent Number Title Of Patent Date Issued
5904531 Method of increasing the area of a buried contact region May. 18, 1999
5899717 Method for fabricating semiconductor device May. 4, 1999
5891770 Method for fabricating a high bias metal oxide semiconductor device Apr. 6, 1999
5882964 Process for the production of an integrated CMOS circuit Mar. 16, 1999
5882983 Trench isolation structure partially bound between a pair of low K dielectric structures Mar. 16, 1999
5879983 Semiconductor device and method for manufacturing the same Mar. 9, 1999
5880006 Method for fabrication of a semiconductor device Mar. 9, 1999
5874317 Trench isolation for integrated circuits Feb. 23, 1999
5874328 Reverse CMOS method for dual isolation semiconductor device Feb. 23, 1999
5874346 Subtrench conductor formation with large tilt angle implant Feb. 23, 1999
5874353 Method of forming a self-aligned silicide device Feb. 23, 1999
5858825 Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETS Jan. 12, 1999
5858830 Method of making dual isolation regions for logic and embedded memory devices Jan. 12, 1999
5858842 Methods of forming combined trench and locos-based electrical isolation regions in semiconductor substrates Jan. 12, 1999
5858866 Geometrical control of device corner threshold Jan. 12, 1999
5854112 Transistor isolation process Dec. 29, 1998
5854114 Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide Dec. 29, 1998
5851881 Method of making monos flash memory for multi-level logic Dec. 22, 1998
5849621 Method and structure for isolating semiconductor devices after transistor formation Dec. 15, 1998
5843816 Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell Dec. 1, 1998
5843824 Diode-based semiconductor read-only memory device and method of fabricating the same Dec. 1, 1998
5837612 Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation Nov. 17, 1998
5834358 Isolation regions and methods of forming isolation regions Nov. 10, 1998
5830796 Method of manufacturing a semiconductor device using trench isolation Nov. 3, 1998
5830797 Interconnect methods and apparatus Nov. 3, 1998
5811347 Nitrogenated trench liner for improved shallow trench isolation Sep. 22, 1998
5804862 Semiconductor device having contact hole open to impurity region coplanar with buried isolating region Sep. 8, 1998
5786262 Self-planarized gapfilling for shallow trench isolation Jul. 28, 1998
5780346 N.sub.2 O nitrided-oxide trench sidewalls and method of making isolation structure Jul. 14, 1998
5770501 Process of fabricating NAND-structure flash EEPROM using liquid phase deposition Jun. 23, 1998
5770504 Method for increasing latch-up immunity in CMOS devices Jun. 23, 1998
5766971 Oxide strip that improves planarity Jun. 16, 1998
5763309 Self-aligned isolation and planarization process for memory array Jun. 9, 1998
5763310 Integrated circuit employing simultaneously formed isolation and transistor trenches Jun. 9, 1998
5763315 Shallow trench isolation with oxide-nitride/oxynitride liner Jun. 9, 1998
5753554 Semiconductor device and method of forming the same May. 19, 1998
5753562 Methods of forming semiconductor devices in substrates having inverted-trench isolation regions therein May. 19, 1998
5753961 Trench isolation structures for a semiconductor device May. 19, 1998
5741738 Method of making corner protected shallow trench field effect transistor Apr. 21, 1998
5731237 Method of producing an EPROM with a trench insulating layer Mar. 24, 1998
5731239 Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance Mar. 24, 1998
5731241 Self-aligned sacrificial oxide for shallow trench isolation Mar. 24, 1998
5728620 Isolation method of semiconductor device Mar. 17, 1998
5728621 Method for shallow trench isolation Mar. 17, 1998
5726084 Method for forming integrated circuit structure Mar. 10, 1998
5721173 Method of forming a shallow trench isolation structure Feb. 24, 1998
5719085 Shallow trench isolation technique Feb. 17, 1998
5693542 Method for forming a transistor with a trench Dec. 2, 1997
5691215 Method for fabricating a sub-half micron MOSFET device with insulator filled shallow trenches planarized via use of negative photoresist and de-focus exposure Nov. 25, 1997
5679591 Method of making raised-bitline contactless trenched flash memory cell Oct. 21, 1997

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