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Class Information
Number: 438/296
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Including isolation structure > Dielectric isolation formed by grooving and refilling with dielectric material
Description: Process for making an insulated gate field effect transistor including the step of forming an isolation structure by making a recess in the semiconductor substrate and refilling the recess with an insulative material.

Patents under this class:
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Patent Number Title Of Patent Date Issued
6168994 Method of making memory device with an element splitting trench Jan. 2, 2001
6169002 Methods of forming trench isolation structures by etching back electrically insulating layers using etching masks Jan. 2, 2001
6165843 Covered slit isolation between integrated circuit devices Dec. 26, 2000
6165853 Trench isolation method Dec. 26, 2000
6165854 Method to form shallow trench isolation with an oxynitride buffer layer Dec. 26, 2000
6159821 Methods for shallow trench isolation Dec. 12, 2000
6156620 Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same Dec. 5, 2000
6153472 Method for fabricating a flash memory Nov. 28, 2000
6153478 STI process for eliminating kink effect Nov. 28, 2000
6153479 Method of fabricating shallow trench isolation structures Nov. 28, 2000
6153480 Advanced trench sidewall oxide for shallow trench technology Nov. 28, 2000
6153494 Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash Nov. 28, 2000
6153918 Semiconductor device with improved planarity and reduced parasitic capacitance Nov. 28, 2000
6150234 Trench-diffusion corner rounding in a shallow-trench (STI) process Nov. 21, 2000
6146970 Capped shallow trench isolation and method of formation Nov. 14, 2000
6146975 Shallow trench isolation Nov. 14, 2000
6140156 Fabrication method of isolation structure photodiode Oct. 31, 2000
6140182 Nonvolatile memory with self-aligned floating gate and fabrication process Oct. 31, 2000
6140193 Method for forming a high-voltage semiconductor device with trench structure Oct. 31, 2000
6140206 Method to form shallow trench isolation structures Oct. 31, 2000
6133105 Method of manufacturing borderless contact hole including a silicide layer on source/drain and sidewall of trench isolation structure Oct. 17, 2000
6130129 Method of making self-aligned stacked gate flush memory with high control gate to floating gate coupling ratio Oct. 10, 2000
6127228 Method of forming buried bit line Oct. 3, 2000
6124156 Process for manufacturing a CMOS circuit with all-around dielectrically insulated source-drain regions Sep. 26, 2000
6117722 SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof Sep. 12, 2000
6117740 Method of forming a shallow trench isolation by using PE-oxide and PE-nitride multi-layer Sep. 12, 2000
6110796 Method of improving junction leakage problem of shallow trench isolation by covering said STI with an insulating layer during salicide process Aug. 29, 2000
6107143 Method for forming a trench isolation structure in an integrated circuit Aug. 22, 2000
6103574 Method of manufacturing non-volatile semiconductor memory device having reduced electrical resistance of a source diffusion layer Aug. 15, 2000
6103577 Method of manufacturing a flash memory structure Aug. 15, 2000
6103581 Method for producing shallow trench isolation structure Aug. 15, 2000
6103588 Method of forming a contact hole in a semiconductor device Aug. 15, 2000
6100143 Method of making a depleted poly-silicon edged MOSFET structure Aug. 8, 2000
6100159 Quasi soi device Aug. 8, 2000
6096604 Production of reversed flash memory device Aug. 1, 2000
6096612 Increased effective transistor width using double sidewall spacers Aug. 1, 2000
6096662 NH.sub.3 /N.sub.2 plasma treatment to enhance the adhesion of silicon nitride to thermal oxide Aug. 1, 2000
6096664 Method of manufacturing semiconductor structures including a pair of MOSFETs Aug. 1, 2000
6093592 Method of manufacturing a semiconductor apparatus having a silicon-on-insulator structure Jul. 25, 2000
6093593 Method of forming a gate which provides a reduced corner recess in adjacent shallow trench isolation Jul. 25, 2000
6093611 Oxide liner for high reliability with reduced encroachment of the source/drain region Jul. 25, 2000
6093618 Method of fabricating a shallow trench isolation structure Jul. 25, 2000
6091129 Self-aligned trench isolated structure Jul. 18, 2000
6087233 Forming trench isolators in semiconductor devices Jul. 11, 2000
6087705 Trench isolation structure partially bound between a pair of low K dielectric structures Jul. 11, 2000
6083797 Buried shallow trench isolation and method for forming the same Jul. 4, 2000
6084276 Threshold voltage tailoring of corner of MOSFET device Jul. 4, 2000
6080628 Method of forming shallow trench isolation for integrated circuit applications Jun. 27, 2000
6080637 Shallow trench isolation technology to eliminate a kink effect Jun. 27, 2000
6077748 Advanced trench isolation fabrication scheme for precision polysilicon gate control Jun. 20, 2000

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