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Class Information
Number: 438/296
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Including isolation structure > Dielectric isolation formed by grooving and refilling with dielectric material
Description: Process for making an insulated gate field effect transistor including the step of forming an isolation structure by making a recess in the semiconductor substrate and refilling the recess with an insulative material.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6461932 Semiconductor trench isolation process that utilizes smoothening layer Oct. 8, 2002
6461935 Method of manufacturing trench-shaped isolator Oct. 8, 2002
6455381 Method of manufacturing a semiconductor device having a trench isolation structure Sep. 24, 2002
6455382 Multi-step method for forming sacrificial silicon oxide layer Sep. 24, 2002
6455383 Methods of fabricating scaled MOSFETs Sep. 24, 2002
6451654 Process for fabricating self-aligned split gate flash memory Sep. 17, 2002
6448606 Semiconductor with increased gate coupling coefficient Sep. 10, 2002
6444515 Method of fabricating a semiconductor device Sep. 3, 2002
6436838 Method of patterning lead zirconium titanate and barium strontium titanate Aug. 20, 2002
6432798 Extension of shallow trench isolation by ion implantation Aug. 13, 2002
6417047 Manufacturing method of a non-volatile semiconductor memory device having isolation regions Jul. 9, 2002
6417054 Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide Jul. 9, 2002
6413809 Method of manufacturing a non-volatile memory having an element isolation insulation film embedded in the trench Jul. 2, 2002
6413826 Gate insulator process for nanometer MOSFETS Jul. 2, 2002
6413827 Low dielectric constant shallow trench isolation Jul. 2, 2002
6413828 Process using poly-buffered STI Jul. 2, 2002
6413836 Method of making isolation trench Jul. 2, 2002
6410405 Method for forming a field oxide film on a semiconductor device including mask spacer and rounding edge Jun. 25, 2002
6406972 Integrated circuit, components thereof and manufacturing method Jun. 18, 2002
6406976 Semiconductor device and process for forming the same Jun. 18, 2002
6406977 Isolation region forming methods Jun. 18, 2002
6403415 Semiconductor device having a metal barrier layer for a dielectric material having a high dielectric constant and a method of manufacture thereof Jun. 11, 2002
6403429 SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A Jun. 11, 2002
6403430 Semiconductor structure having more usable substrate area and method for forming same Jun. 11, 2002
6403431 Method of forming in an insulating layer a trench that exceeds the photolithographic resolution limits Jun. 11, 2002
6403432 Hardmask for a salicide gate process with trench isolation Jun. 11, 2002
6399449 Semiconductor circuit using trench isolation and method of fabrication a trench isolator Jun. 4, 2002
6391720 Process flow for a performance enhanced MOSFET with self-aligned, recessed channel May. 21, 2002
6391722 Method of making nonvolatile memory having high capacitive coupling ratio May. 21, 2002
6391729 Shallow trench isolation formation to eliminate poly stringer with controlled step height and corner rounding May. 21, 2002
6391739 Process of eliminating a shallow trench isolation divot May. 21, 2002
6387764 Trench isolation process to deposit a trench fill oxide prior to sidewall liner oxidation growth May. 14, 2002
6387776 Method for forming trench isolation regions May. 14, 2002
6388303 Semiconductor device and semiconductor device manufacture method May. 14, 2002
6383837 Method of manufacturing a multi-chip semiconductor device effective to improve alignment May. 7, 2002
6383877 Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer May. 7, 2002
6380027 Dual tox trench dram structures and process using V-groove Apr. 30, 2002
6380063 Raised wall isolation device with spacer isolated contacts and the method of so forming Apr. 30, 2002
6376299 Capacitor for semiconductor memory device and method of manufacturing the same Apr. 23, 2002
6376316 Method for manufacturing semiconductor integrated circuit device having deposited layer for gate insulation Apr. 23, 2002
6372584 Method for making raised source/drain regions using laser Apr. 16, 2002
6372602 Method of forming a shallow trench isolation structure in a semiconductor device Apr. 16, 2002
6368931 Thin tensile layers in shallow trench isolation and method of making same Apr. 9, 2002
6365468 Method for forming doped p-type gate with anti-reflection layer Apr. 2, 2002
6362074 Integrated circuit processing with improved gate electrode fabrication Mar. 26, 2002
6358801 Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination Mar. 19, 2002
6352897 Method of improving edge recess problem of shallow trench isolation Mar. 5, 2002
6350654 Semiconductor read-only memory device and method of fabricating the same Feb. 26, 2002
6350655 Semiconductor device and a method of manufacturing the same Feb. 26, 2002
6350660 Process for forming a shallow trench isolation Feb. 26, 2002

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