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Class Information
Number: 438/296
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Including isolation structure > Dielectric isolation formed by grooving and refilling with dielectric material
Description: Process for making an insulated gate field effect transistor including the step of forming an isolation structure by making a recess in the semiconductor substrate and refilling the recess with an insulative material.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6348395 |
Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow |
Feb. 19, 2002 |
| 6342431 |
Method for eliminating transfer gate sacrificial oxide |
Jan. 29, 2002 |
| 6339004 |
Method of forming shallow trench isolation for preventing torn oxide |
Jan. 15, 2002 |
| 6335249 |
Salicide field effect transistors with improved borderless contact structures and a method of fabrication |
Jan. 1, 2002 |
| 6333232 |
Semiconductor device and method of manufacturing the same |
Dec. 25, 2001 |
| 6333218 |
Method of etching contacts with reduced oxide stress |
Dec. 25, 2001 |
| 6331469 |
Trench isolation structure, semiconductor device having the same, and trench isolation method |
Dec. 18, 2001 |
| 6329271 |
Self-aligned channel implantation |
Dec. 11, 2001 |
| 6326283 |
Trench-diffusion corner rounding in a shallow-trench (STI) process |
Dec. 4, 2001 |
| 6323143 |
Method for making silicon nitride-oxide ultra-thin gate insulating layers for submicrometer field effect transistors |
Nov. 27, 2001 |
| 6323112 |
Method of fabricating integrated circuits |
Nov. 27, 2001 |
| 6323092 |
Method for forming a shallow trench isolation |
Nov. 27, 2001 |
| 6323082 |
Process for making a DRAM cell with three-sided gate transfer |
Nov. 27, 2001 |
| 6319860 |
Process for manufacturing semiconductor integrated circuit device including treatment of gas used in the process |
Nov. 20, 2001 |
| 6316330 |
Method of fabricating a shallow trench isolation semiconductor device |
Nov. 13, 2001 |
| 6316815 |
Structure for isolating integrated circuits in semiconductor substrate and method for making it |
Nov. 13, 2001 |
| 6313008 |
Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon |
Nov. 6, 2001 |
| 6309949 |
Semiconductor isolation process to minimize weak oxide problems |
Oct. 30, 2001 |
| 6309939 |
Method of manufacturing a semiconductor device |
Oct. 30, 2001 |
| 6306737 |
Method to reduce source-line resistance in flash memory with sti |
Oct. 23, 2001 |
| 6303462 |
Process for physical isolation of regions of a substrate board |
Oct. 16, 2001 |
| 6303413 |
Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates |
Oct. 16, 2001 |
| 6300204 |
Semiconductor processing methods of forming integrated circuitry, conductive lines, a conductive grid, a conductive network, an electrical interconnection to a node location, and an electrical |
Oct. 9, 2001 |
| 6297082 |
Method of fabricating a MOS transistor with local channel ion implantation regions |
Oct. 2, 2001 |
| 6294481 |
Semiconductor device and method for manufacturing the same |
Sep. 25, 2001 |
| 6294419 |
Structure and method for improved latch-up using dual depth STI with impurity implant |
Sep. 25, 2001 |
| 6294817 |
Source/drain-on insulator (S/DOI) field effect transistor using oxidized amorphous silicon and method of fabrication |
Sep. 25, 2001 |
| 6291300 |
Manufacturing method of semiconductor devices |
Sep. 18, 2001 |
| 6287921 |
Method of performing threshold voltage adjustment for MOS transistors |
Sep. 11, 2001 |
| 6281082 |
Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill |
Aug. 28, 2001 |
| 6281081 |
Method of preventing current leakage around a shallow trench isolation structure |
Aug. 28, 2001 |
| 6281093 |
Method to reduce trench cone formation in the fabrication of shallow trench isolations |
Aug. 28, 2001 |
| 6281103 |
Method for fabricating gate semiconductor |
Aug. 28, 2001 |
| 6277697 |
Method to reduce inverse-narrow-width effect |
Aug. 21, 2001 |
| 6277707 |
Method of manufacturing semiconductor device having a recessed gate structure |
Aug. 21, 2001 |
| 6274434 |
Method of making memory cell with shallow trench isolation |
Aug. 14, 2001 |
| 6271093 |
Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETs |
Aug. 7, 2001 |
| 6268264 |
Method of forming shallow trench isolation |
Jul. 31, 2001 |
| 6265285 |
Method of forming a self-aligned trench isolation |
Jul. 24, 2001 |
| 6265271 |
Integration of the borderless contact salicide process |
Jul. 24, 2001 |
| 6265282 |
Process for making an isolation structure |
Jul. 24, 2001 |
| 6265284 |
Method of manufacturing a trench isolation region in a semiconductor device |
Jul. 24, 2001 |
| 6261905 |
Flash memory structure with stacking gate formed using damascene-like structure |
Jul. 17, 2001 |
| 6261924 |
Maskless process for self-aligned contacts |
Jul. 17, 2001 |
| 6258676 |
Method for forming a shallow trench isolation using HDP silicon oxynitride |
Jul. 10, 2001 |
| 6255176 |
Method of forming trench for semiconductor device isolation |
Jul. 3, 2001 |
| 6251735 |
Method of forming shallow trench isolation structure |
Jun. 26, 2001 |
| 6251749 |
Shallow trench isolation formation with sidewall spacer |
Jun. 26, 2001 |
| 6251734 |
Method for fabricating trench isolation and trench substrate contact |
Jun. 26, 2001 |
| 6251747 |
Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices |
Jun. 26, 2001 |
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