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Class Information
Number: 438/280
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Having underpass or crossunder
Description: Process for making an insulated gate field effect transistor electrically interconnected to an adjoining electrical device via a conductive structure located within the semiconductor substrate.

Patents under this class:
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Patent Number Title Of Patent Date Issued
8709896 Semiconductor device and fabrication method Apr. 29, 2014
8237287 Semiconductor device Aug. 7, 2012
8097514 Method for an integrated circuit contact Jan. 17, 2012
8058114 Method of manufacturing the array substrate capable of decreasing a line resistance Nov. 15, 2011
8053846 Field effect transistor (FET) having nano tube and method of manufacturing the FET Nov. 8, 2011
8022501 Semiconductor device and method for isolating the same Sep. 20, 2011
7977749 Semiconductor device with increased channel area Jul. 12, 2011
7977196 Semiconductor device with increased channel area and fabrication method thereof Jul. 12, 2011
7973360 Depletable cathode low charge storage diode Jul. 5, 2011
7919378 Transistor and method of forming the same Apr. 5, 2011
7868461 Embedded interconnects, and methods for forming same Jan. 11, 2011
7863140 Methods of making a molecular detection chip having a metal oxide silicon field effect transistor on sidewalls of a micro-fluid channel Jan. 4, 2011
7833842 Mixed-scale electronic interface Nov. 16, 2010
7812451 Semiconductor device and method of manufacturing the same Oct. 12, 2010
7800197 Semiconductor device and method of fabricating the same Sep. 21, 2010
7759728 Depletable cathode low charge storage diode Jul. 20, 2010
7741184 Fin device with capacitor integrated under gate electrode Jun. 22, 2010
7638398 Semiconductor device with increased channel area and fabrication method thereof Dec. 29, 2009
7540970 Methods of fabricating a semiconductor device Jun. 2, 2009
7479410 Hybrid-orientation technology buried n-well design Jan. 20, 2009
7462539 Direct tunneling memory with separated transistor and tunnel areas Dec. 9, 2008
7396726 Methods of fabricating surrounded-channel transistors with directionally etched gate or insulator formation regions Jul. 8, 2008
7385246 Depletable cathode low charge storage diode Jun. 10, 2008
7338840 Method of forming a semiconductor die with heat and electrical pipes Mar. 4, 2008
6897103 MOS integrated circuit with reduced on resistance May. 24, 2005
6893916 Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same May. 17, 2005
6847084 Semiconductor device Jan. 25, 2005
6784019 Intercrossedly-stacked dual-chip semiconductor package and method of fabricating the same Aug. 31, 2004
RE38565 Thin film ferroelectric capacitors having improved memory retention through the use of essentially smooth bottom electrode structures Aug. 17, 2004
6740571 Method of etching a dielectric material in the presence of polysilicon May. 25, 2004
6677202 Power MOS device with increased channel width and process for forming same Jan. 13, 2004
6674132 Memory cell and production method Jan. 6, 2004
6635518 SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies Oct. 21, 2003
6566197 Method for fabricating connection structure between segment transistor and memory cell region of flash memory device May. 20, 2003
6541298 Method of making infrared sensor with a thermoelectric converting portion Apr. 1, 2003
6541330 Capacitor for semiconductor memory device and method of manufacturing the same Apr. 1, 2003
6509217 Inexpensive, reliable, planar RFID tag structure and method for making same Jan. 21, 2003
6503787 Device and method for forming semiconductor interconnections in an integrated circuit substrate Jan. 7, 2003
6440754 Thin film ferroelectric capacitors having improved memory retention through the use of essentially smooth bottom electrode structures Aug. 27, 2002
6436765 Method of fabricating a trenched flash memory cell Aug. 20, 2002
6403424 Method for forming self-aligned mask read only memory by dual damascene trenches Jun. 11, 2002
6387788 Method for forming polycide gate electrode of metal oxide semiconductor field effect transistor May. 14, 2002
6340628 Method to deposit SiOCH films with dielectric constant below 3.0 Jan. 22, 2002
6291863 Thin film transistor having a multi-layer stacked channel and its manufacturing method Sep. 18, 2001
6261908 Buried local interconnect Jul. 17, 2001
6204107 Method for forming multi-layered liner on sidewall of node contact opening Mar. 20, 2001
6153467 Method of fabricating high density buried bit line flash EEPROM memory cell with a shallow trench floating gate Nov. 28, 2000
6104069 Semiconductor device having an elevated active region formed in an oxide trench Aug. 15, 2000
6037225 Manufacturing method for mask ROM devices Mar. 14, 2000
5952697 Multiple storage planes Read Only Memory integrated circuit device Sep. 14, 1999

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