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Class Information
Number: 438/276
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Making plural insulated gate field effect transistors of differing electrical characteristics > Introducing a dopant into the channel region of selected transistors
Description: Process for making plural insulated gate field effect transistors having a step of introducing an electrically active dopant species into the semiconductor channel region beneath the gate insulator of one or more transistors to produce transistors of differing electrical characteristics.










Sub-classes under this class:

Class Number Class Name Patents
438/278 After formation of source or drain regions and gate electrode (e.g., late programming, encoding, etc.) 297
438/277 Including forming overlapping gate electrodes 58


Patents under this class:
1 2 3 4 5 6 7 8

Patent Number Title Of Patent Date Issued
7385232 CMOS imager with enhanced transfer of charge and low voltage operation and method of formation Jun. 10, 2008
7354817 Semiconductor device, manufacturing method thereof, and CMOS integrated circuit device Apr. 8, 2008
7352035 Flash memory devices and methods for fabricating flash memory devices Apr. 1, 2008
7329569 Methods of forming semiconductor devices including mesa structures and multiple passivation layers Feb. 12, 2008
7314800 Application of different isolation schemes for logic and embedded memory Jan. 1, 2008
7265012 Formation of standard voltage threshold and low voltage threshold MOSFET devices Sep. 4, 2007
7259054 Method of manufacturing a semiconductor device that includes a process for forming a high breakdown voltage field effect transistor Aug. 21, 2007
7230877 Method of making a semiconductor memory device Jun. 12, 2007
7217606 Method of forming vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, soi and thin film structures May. 15, 2007
7186619 Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET Mar. 6, 2007
7115462 Processes providing high and low threshold p-type and n-type transistors Oct. 3, 2006
7115471 Method of manufacturing semiconductor device including nonvolatile memory Oct. 3, 2006
7091093 Method for fabricating a semiconductor device having a pocket dopant diffused layer Aug. 15, 2006
7049189 Method of fabricating non-volatile memory cell adapted for integration of devices and for multiple read/write operations May. 23, 2006
7015535 Nonvolatile semiconductor memory device Mar. 21, 2006
7008848 Mask ROM fabrication method Mar. 7, 2006
6998316 Method for fabricating read only memory including a first and second exposures to a photoresist layer Feb. 14, 2006
6979609 Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks Dec. 27, 2005
6969642 Method of controlling implantation dosages during coding of read-only memory devices Nov. 29, 2005
6933188 Use of a selective hard mask for the integration of double diffused drain MOS devices in deep sub-micron fabrication technologies Aug. 23, 2005
6919607 Structure of two-bit mask read-only memory device and fabricating method thereof Jul. 19, 2005
6916713 Code implantation process Jul. 12, 2005
6916716 Asymmetric halo implants Jul. 12, 2005
6900101 LDMOS transistors and methods for making the same May. 31, 2005
6888202 Low-power high-performance storage circuitry May. 3, 2005
6879007 Low volt/high volt transistor Apr. 12, 2005
6870233 Multi-bit ROM cell with bi-directional read and a method for making thereof Mar. 22, 2005
6867085 Insulated gate semiconductor device and method of manufacturing the same Mar. 15, 2005
6861372 Semiconductor device manufacturing method Mar. 1, 2005
6835622 Gate electrode doping method for forming semiconductor integrated circuit microelectronic fabrication with varying effective gate dielectric layer thicknesses Dec. 28, 2004
6828197 Method for fabricating nitride read only memory Dec. 7, 2004
6818494 LDMOS and CMOS integrated circuit and method of making Nov. 16, 2004
6815768 Semiconductor integrated circuit device incorporating memory cell transistor and logic transistor, and method of manufacturing the same Nov. 9, 2004
6812085 Semiconductor device and method for fabricating same Nov. 2, 2004
6808990 Random access memory cell and method for fabricating same Oct. 26, 2004
6803282 Methods for fabricating low CHC degradation mosfet transistors Oct. 12, 2004
6803285 Method of fabricating dual threshold voltage n-channel and p-channel mosfets with a single extra masked implant operation Oct. 12, 2004
6794253 Mask ROM structure and method of fabricating the same Sep. 21, 2004
6780697 Method of manufacturing lateral double-diffused metal oxide semiconductor device Aug. 24, 2004
6780698 Semiconductor device and its production method Aug. 24, 2004
6780717 Semiconductor integrated circuit device and method of manufacturing the same Aug. 24, 2004
6773972 Memory cell with transistors having relatively high threshold voltages in response to selective gate doping Aug. 10, 2004
6762100 Mask ROM cell and method of fabricating the same Jul. 13, 2004
6753230 Method for fabricating semiconductor device with ultra-shallow super-steep-retrograde epi-channel by decaborane doping Jun. 22, 2004
6734064 Method for fabricating read only memory including forming masking layers with openings and pre-coding the cell and peripheral regions May. 11, 2004
6730568 Method for fabricating semiconductor device with ultra-shallow super-steep-retrograde epi-channel by boron-fluoride compound doping May. 4, 2004
6730555 Transistors having selectively doped channel regions May. 4, 2004
6720210 Mask ROM structure and manufacturing method thereof Apr. 13, 2004
6717208 Disabling flash memory to protect memory contents Apr. 6, 2004
6713821 Structure of a mask ROM device Mar. 30, 2004

1 2 3 4 5 6 7 8










 
 
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