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Class Information
Number: 438/271
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Vertical channel > Gate electrode in trench or recess in semiconductor substrate > V-gate
Description: Process for making an insulated gate field effect transistor wherein the gate electrode has a V-shape configuration.
Patents under this class:
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Title Of Patent |
Date Issued |
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Integrated circuit devices providing improved short prevention |
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Electrical detection of V-groove width |
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UMOS-like gate-controlled thyristor structure for ESD protection |
Oct. 1, 2002 |
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Dual tox trench dram structures and process using V-groove |
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Method of forming a trench DMOS having reduced threshold voltage |
Apr. 23, 2002 |
| 6365462 |
Methods of forming power semiconductor devices having tapered trench-based insulating regions therein |
Apr. 2, 2002 |
| 6344379 |
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Jan. 29, 2002 |
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Nov. 27, 2001 |
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Nov. 20, 2001 |
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Method of manufacturing vertical trench misfet |
Jan. 16, 2001 |
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Short channel non-self aligned VMOS field effect transistor |
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Low and high voltage CMOS devices and process for fabricating same |
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Production method of a vertical type MOSFET |
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Vertically oriented structure with sloped opening and method for etching |
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Insulated gate semiconductor device |
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Dec. 7, 1999 |
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Localized lattice-mismatch-accomodation dislocation network epitaxy |
Dec. 7, 1999 |
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Short channel self-aligned VMOS field effect transistor |
Sep. 28, 1999 |
| 5893736 |
Methods of forming insulated gate semiconductor devices having spaced epitaxial JFET regions therein |
Apr. 13, 1999 |
| 5811336 |
Method of forming MOS transistors having gate insulators of different thicknesses |
Sep. 22, 1998 |
| 5786244 |
Method for making GaAs-InGaAs high electron mobility transistor |
Jul. 28, 1998 |
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