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Class Information
Number: 438/266
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Having additional gate electrode surrounded by dielectric (i.e., floating gate) > Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.)
Description: Process for making a floating gate-type field effect transistor having an additional, nonmemory control electrode (i.e., having direct electrical contact thereto) or channel portion.

Sub-classes under this class:

Class Number Class Name Patents
438/267 Including forming gate electrode as conductive sidewall spacer to another electrode 413

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Patent Number Title Of Patent Date Issued
6159800 Method of forming a memory cell Dec. 12, 2000
6159795 Low voltage junction and high voltage junction optimization for flash memory Dec. 12, 2000
6156610 Process for manufacturing an EEPROM having a peripheral transistor with thick oxide Dec. 5, 2000
6157058 Low voltage EEPROM/NVRAM transistors and making method Dec. 5, 2000
6143609 Method for forming semiconductor memory device Nov. 7, 2000
6143606 Method for manufacturing split-gate flash memory cell Nov. 7, 2000
6136658 Method of fabricating a semiconductor device including a contact hole between gate electrode structures Oct. 24, 2000
6136648 Nonvolatile semiconductor memory device and a method of fabricating the same Oct. 24, 2000
6136653 Method and device for producing undercut gate for flash memory Oct. 24, 2000
6136650 Method of forming three-dimensional flash memory structure Oct. 24, 2000
6136652 Preventing dielectric thickening over a channel area of a split-gate transistor Oct. 24, 2000
6133097 Method for forming mirror image split gate flash memory devices by forming a central source line slot Oct. 17, 2000
6130134 Method for forming asymmetric flash EEPROM with a pocket to focus electron injections Oct. 10, 2000
6130129 Method of making self-aligned stacked gate flush memory with high control gate to floating gate coupling ratio Oct. 10, 2000
6127225 Memory cell having implanted region formed between select and sense transistors Oct. 3, 2000
6127224 Process for forming a non-volatile memory cell with silicided contacts Oct. 3, 2000
6127704 Structure of SRAM cell and method for fabricating the same Oct. 3, 2000
6127229 Process of forming an EEPROM device having a split gate Oct. 3, 2000
6124157 Integrated non-volatile and random access memory and method of forming the same Sep. 26, 2000
6096602 Method for fabricating flash memory cell Aug. 1, 2000
6096603 Method of fabricating a split gate structure of a flash memory Aug. 1, 2000
6096604 Production of reversed flash memory device Aug. 1, 2000
6096605 Fabricating method of non-volatile flash memory device Aug. 1, 2000
6093608 Source side injection programming and tip erasing P-channel split gate flash memory cell Jul. 25, 2000
6093607 Method of forming sharp beak of poly by oxygen/fluorine implant to improve erase speed for split-gate flash Jul. 25, 2000
6090668 Method to fabricate sharp tip of poly in split gate flash Jul. 18, 2000
6087221 Method of fabricating two dissimilar devices with diminished processing steps Jul. 11, 2000
6083792 Manufacturing process of a split gate flash memory unit Jul. 4, 2000
6071776 Flash memory structure and method of manufacture Jun. 6, 2000
6071778 Memory device with a memory cell array in triple well, and related manufacturing process Jun. 6, 2000
6069042 Multi-layer spacer technology for flash EEPROM May. 30, 2000
6060346 Semiconductor device and method for manufacturing the same May. 9, 2000
6060356 Method of fabricating virtual ground SSI flash EPROM cell and array May. 9, 2000
6057193 Elimination of poly cap for easy poly1 contact for NAND product May. 2, 2000
6046086 Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash Apr. 4, 2000
6040210 2F-square memory cell for gigabit memory applications Mar. 21, 2000
6030868 Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation Feb. 29, 2000
6030869 Method for fabricating nonvolatile semiconductor memory device Feb. 29, 2000
6027974 Nonvolatile memory Feb. 22, 2000
6023085 Core cell structure and corresponding process for NAND-type high performance flash memory device Feb. 8, 2000
6020223 Method of manufacturing a thin film transistor with reduced parasitic capacitance and reduced feed-through voltage Feb. 1, 2000
6017795 Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash Jan. 25, 2000
6015984 Capacitor with oxide/nitride/oxide composite dielectric suitable for embedded nonvolatile memory in analog applications Jan. 18, 2000
6013552 Method of manufacturing a split-gate flash memory cell Jan. 11, 2000
6008091 Floating gate avalanche injection MOS transistors with high K dielectric control gates Dec. 28, 1999
6008088 Method for fabricating a semiconductor memory device Dec. 28, 1999
6008089 Method of fabricating a split gate flash memory device Dec. 28, 1999
6001713 Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device Dec. 14, 1999
6001690 Method of forming flash EPROM by using iso+aniso silicon nitride spacer etching technology Dec. 14, 1999
6001689 Process for fabricating a flash memory with dual function control lines Dec. 14, 1999

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

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