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Class Information
Number: 438/258
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Having additional gate electrode surrounded by dielectric (i.e., floating gate) > Including additional field effect transistor (e.g., sense or access transistor, etc.)
Description: Process for making a floating gate-type insulated gate field effect transistor having combined therewith an additional field effect transistor.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5081054 |
Fabrication process for programmable and erasable MOS memory device |
Jan. 14, 1992 |
| 5057448 |
Method of making a semiconductor device having DRAM cells and floating gate memory cells |
Oct. 15, 1991 |
| 5049515 |
Method of making a three-dimensional memory cell with integral select transistor |
Sep. 17, 1991 |
| 5045489 |
Method of making a high-speed 2-transistor cell for programmable/EEPROM devices with separate read and write transistors |
Sep. 3, 1991 |
| 5013674 |
A method of manufacturing integrated circuits comprising EPROM memory and logic transistors |
May. 7, 1991 |
| 4997777 |
Manufacturing process for an integrated circuit comprising double gate components |
Mar. 5, 1991 |
| 4988635 |
Method of manufacturing non-volatile semiconductor memory device |
Jan. 29, 1991 |
| 4975383 |
Method for making an electrically erasable programmable read only memory cell having a three dimensional floating gate |
Dec. 4, 1990 |
| 4975384 |
Erasable electrically programmable read only memory cell using trench edge tunnelling |
Dec. 4, 1990 |
| 4931411 |
Integrated circuit process with TiN-gate transistor |
Jun. 5, 1990 |
| 4859619 |
EPROM fabrication process forming tub regions for high voltage devices |
Aug. 22, 1989 |
| 4833096 |
EEPROM fabrication process |
May. 23, 1989 |
| 4822750 |
MOS floating gate memory cell containing tunneling diffusion region in contact with drain and extending under edges of field oxide |
Apr. 18, 1989 |
| 4818718 |
Method of manufacturing semiconductor memory device |
Apr. 4, 1989 |
| 4808261 |
Fabrication process for EPROM cells with oxide-nitride-oxide dielectric |
Feb. 28, 1989 |
| 4780431 |
Process for making structures including E2PROM nonvolatile memory cells with self-aligned layers of silicon and associated transistors |
Oct. 25, 1988 |
| 4775642 |
Modified source/drain implants in a double-poly non-volatile memory process |
Oct. 4, 1988 |
| 4766088 |
Method of making a memory device with polysilicon electrodes |
Aug. 23, 1988 |
| 4764479 |
Semiconductor integrated circuit device and method of manufacturing the same |
Aug. 16, 1988 |
| 4719184 |
Process for the fabrication of integrated structures including nonvolatile memory cells with layers of self-aligned silicon and associated transistors |
Jan. 12, 1988 |
| 4651406 |
Forming memory transistors with varying gate oxide thicknesses |
Mar. 24, 1987 |
| 4495693 |
Method of integrating MOS devices of double and single gate structure |
Jan. 29, 1985 |
| 4490900 |
Method of fabricating an MOS memory array having electrically-programmable and electrically-erasable storage devices incorporated therein |
Jan. 1, 1985 |
| 4426764 |
Semiconductor memory device with peripheral circuits |
Jan. 24, 1984 |
| 4420871 |
Method of producing a monolithically integrated two-transistor memory cell in accordance with MOS technology |
Dec. 20, 1983 |
| 4417325 |
Highly scaleable dynamic ram cell with self-signal amplification |
Nov. 22, 1983 |
| 4373249 |
Method of manufacturing a semiconductor integrated circuit device |
Feb. 15, 1983 |
| 4302766 |
Self-limiting erasable memory cell with triple level polysilicon |
Nov. 24, 1981 |
| 4295265 |
Method for producing a nonvolatile semiconductor memory |
Oct. 20, 1981 |
| 4131983 |
Adjustment of avalanche voltage in DIFMOS memory devices by control of impurity doping |
Jan. 2, 1979 |
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