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Class Information
Number: 438/241
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Including passive device (e.g., resistor, capacitor, etc.) > Capacitor > And additional field effect transistor (e.g., sense or access transistor, etc.)
Description: Process for making an insulated gate field effect transistor having combined therewith a capacitor and an additional field effect transistor.










Sub-classes under this class:

Class Number Class Name Patents
438/242 Including transistor formed on trench sidewalls 303


Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Patent Number Title Of Patent Date Issued
6281066 Method of manufacturing a capacitor in a memory device Aug. 28, 2001
6281067 Self-aligned silicide process for forming silicide layer over word lines in DRAM and transistors in logic circuit region Aug. 28, 2001
6281073 Method for fabricating dynamic random access memory cell Aug. 28, 2001
6281058 Method of forming DRAM circuitry on a semiconductor substrate Aug. 28, 2001
6277686 PIP capacitor for split-gate flash process Aug. 21, 2001
6274425 Method for manufacturing semiconductor device Aug. 14, 2001
6271078 Simplifying conductive plate/via isolation Aug. 7, 2001
6268243 Method for fabricating dynamic random access memory cells Jul. 31, 2001
6261972 Dual gate oxide process for uniform oxide thickness Jul. 17, 2001
6261898 Method for fabricating a salicide gate Jul. 17, 2001
6261897 Method of manufacturing a semiconductor device Jul. 17, 2001
6261896 Memory device and method of forming the same Jul. 17, 2001
6261894 Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays Jul. 17, 2001
6258649 Semiconductor integrated circuit device and method of manufacturing the same Jul. 10, 2001
6258640 Semiconductor device manufacturing method Jul. 10, 2001
6255160 Cell design and process for making dynamic random access memory (DRAM) having one or more Gigabits of memory cells Jul. 3, 2001
6255155 Nonvolatile memory and method for fabricating the same Jul. 3, 2001
6255151 Semiconductor integrated circuit device and method of manufacturing same Jul. 3, 2001
6251719 Poly gate process that provides a novel solution to fix poly-2 residue under poly-1 oxide for charge coupled devices Jun. 26, 2001
6251721 Semiconductor device and method of manufacturing the same Jun. 26, 2001
6248623 Method for manufacturing embedded memory with different spacer widths Jun. 19, 2001
6248645 Semiconductor device having buried-type element isolation structure and method of manufacturing the same Jun. 19, 2001
6242300 Mixed mode process for embedded dram devices Jun. 5, 2001
6239010 Method for manually manufacturing capacitor May. 29, 2001
6235574 High performance DRAM and method of manufacture May. 22, 2001
6235573 Methods of forming ferroelectric random access memory devices having shared capacitor electrodes May. 22, 2001
6235575 Semiconductor device and method for manufacturing same May. 22, 2001
6232195 Structure of semiconductor device May. 15, 2001
6232168 Memory circuitry and method of forming memory circuitry May. 15, 2001
6228704 Process for manufacturing semiconductor integrated circuit device May. 8, 2001
6228703 Method of fabricating mixed-mode semiconductor device having a capacitor and a gate May. 8, 2001
6228697 Method of manufacturing semiconductor device including field effect transistors May. 8, 2001
6221713 Approach for self-aligned contact and pedestal Apr. 24, 2001
6221714 Method of forming a contact hole in a semiconductor substrate using oxide spacers on the sidewalls of the contact hole Apr. 24, 2001
6218234 Dual gate and double poly capacitor analog process integration Apr. 17, 2001
6218259 Capacitor and method for forming the same Apr. 17, 2001
6218235 Method of manufacturing a DRAM and logic device Apr. 17, 2001
6214662 Forming self-align source line for memory array Apr. 10, 2001
6214656 Partial silicide gate in sac (self-aligned contact) process Apr. 10, 2001
6207500 DRAM chip fabrication method Mar. 27, 2001
6207490 Semiconductor device and method for fabricating the same Mar. 27, 2001
6207491 Method for preventing silicon substrate loss in fabricating semiconductor device Mar. 27, 2001
6207492 Common gate and salicide word line process for low cost embedded DRAM devices Mar. 27, 2001
6204115 Manufacture of high-density pillar memory cell arrangement Mar. 20, 2001
6204076 Semiconductor device with unbreakable testing elements for evaluating components and process of fabrication thereof Mar. 20, 2001
6200855 Semiconductor memory device, and method for fabricating thereof Mar. 13, 2001
6200850 Method for forming a stacked capacitor Mar. 13, 2001
6200849 Methods of fabricating conductive contacts for integrated circuit memory devices using first and second dielectric layers and first and second conductive layers Mar. 13, 2001
6200848 Method of fabricating self-aligned contact in embedded DRAM Mar. 13, 2001
6197632 Method for dual sidewall oxidation in high density, high performance DRAMS Mar. 6, 2001

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