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Class Information
Number: 438/233
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Complementary insulated gate field effect transistors (i.e., cmos) > And contact formation
Description: Process for making complementary insulated gate field effect transistors including a step of forming electrical connections to the transistors.










Patents under this class:
1 2 3 4 5 6 7 8 9

Patent Number Title Of Patent Date Issued
5714394 Method of making an ultra high density NAND gate using a stacked transistor arrangement Feb. 3, 1998
5683941 Self-aligned polycide process that utilizes a planarized layer of material to expose polysilicon structures to a subsequently deposited metal layer that is reacted to form the metal silicide Nov. 4, 1997
5679589 FET with gate spacer Oct. 21, 1997
5670424 Method for making local interconnect structure Sep. 23, 1997
5671397 Sea-of-cells array of transistors Sep. 23, 1997
5668024 CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process Sep. 16, 1997
5665630 Device separation structure and semiconductor device improved in wiring structure Sep. 9, 1997
5663086 Method of forming a semiconductor device having CMOS structures on a semiconductor substrate Sep. 2, 1997
5656519 Method for manufacturing salicide semiconductor device Aug. 12, 1997
5654241 Method for manufacturing a semiconductor device having reduced resistance of diffusion layers and gate electrodes Aug. 5, 1997
5652183 Method for fabricating semiconductor device containing excessive silicon in metal silicide film Jul. 29, 1997
5652166 Process for fabricating dual-gate CMOS having in-situ nitrogen-doped polysilicon by rapid thermal chemical vapor deposition Jul. 29, 1997
5637525 Method of forming a CMOS circuitry Jun. 10, 1997
5635426 Method of making a semiconductor device having a silicide local interconnect Jun. 3, 1997
5629224 Resist/etchback planarizing techniques for fabricating semiconductor devices based on CMOS structures May. 13, 1997
5629235 Method for forming damage-free buried contact May. 13, 1997
5620920 Process for fabricating a CMOS structure with ESD protection Apr. 15, 1997
5620919 Methods for fabricating integrated circuits including openings to transistor regions Apr. 15, 1997
5612243 Polycide local interconnect method and structure Mar. 18, 1997
5612245 Method of manufacturing CMOS device Mar. 18, 1997
5605861 Thin polysilicon doping by diffusion from a doped silicon dioxide film Feb. 25, 1997
5604143 Method for producing nonvolatile memory used as read-only storage media Feb. 18, 1997
5589415 Method for forming a semiconductor structure with self-aligned contacts Dec. 31, 1996
5573969 Method for fabrication of CMOS devices having minimized drain contact area Nov. 12, 1996
5571735 Method of manufacturing a semiconducter device capable of easily forming metal silicide films on source and drain regions Nov. 5, 1996
5571753 Method for forming a wiring conductor in semiconductor device Nov. 5, 1996
5563093 Method of manufacturing fet semiconductor devices with polysilicon gate having large grain sizes Oct. 8, 1996
5554565 Modified BP-TEOS tungsten-plug contact process Sep. 10, 1996
5550079 Method for fabricating silicide shunt of dual-gate CMOS device Aug. 27, 1996
5527722 Method of fabrication of a semiconductor device having high-and low-voltage MOS transistors Jun. 18, 1996
5523242 Method of manufacturing a BiMOS device Jun. 4, 1996
5512497 Method of manufacturing a semiconductor integrated circuit device Apr. 30, 1996
5494842 Method of programming a CMOS read only memory at the second metal layer in a two-metal process Feb. 27, 1996
5486482 Process for fabricating metal-gate CMOS transistor Jan. 23, 1996
5472887 Method of fabricating semiconductor device having high-and low-voltage MOS transistors Dec. 5, 1995
5449637 Method of producing low and high voltage MOSFETs with reduced masking steps Sep. 12, 1995
5429958 Process for forming twin well CMOS integrated circuits Jul. 4, 1995
5422308 Method of fabricating a tungsten contact Jun. 6, 1995
5420057 Simplified contact method for high density CMOS May. 30, 1995
5418179 Process of fabricating complementary inverter circuit having multi-level interconnection May. 23, 1995
5387535 Method of fabricating semiconductor devices in CMOS technology with local interconnects Feb. 7, 1995
5382532 Method for fabricating CMOS semiconductor devices Jan. 17, 1995
5372956 Method for making direct contacts in high density MOS/CMOS processes Dec. 13, 1994
5369055 Method for fabricating titanium silicide contacts Nov. 29, 1994
5355010 Semiconductor device with a dual type polycide layer comprising a uniformly p-type doped silicide Oct. 11, 1994
5341014 Semiconductor device and a method of fabricating the same Aug. 23, 1994
5336637 Silicide interconnection with Schottky barrier diode isolation Aug. 9, 1994
5328864 Method of doping gate electrodes discretely with either P-type or N-type impurities to form discrete semiconductor regions Jul. 12, 1994
5306667 Process for forming a novel buried interconnect structure for semiconductor devices Apr. 26, 1994
5302539 VLSI interconnect method and structure Apr. 12, 1994

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