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Class Information
Number: 438/233
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Complementary insulated gate field effect transistors (i.e., cmos) > And contact formation
Description: Process for making complementary insulated gate field effect transistors including a step of forming electrical connections to the transistors.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6383857 Semiconductor device and method for manufacturing the same May. 7, 2002
6380023 Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits Apr. 30, 2002
6373083 Capacitor for semiconductor device and fabrication method thereof Apr. 16, 2002
6372569 Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance Apr. 16, 2002
6368960 Double sidewall raised silicided source/drain CMOS transistor Apr. 9, 2002
6369430 Method of preventing two neighboring contacts from a short-circuit caused by a void between them and device having the same Apr. 9, 2002
6368922 Internal ESD protection structure with contact diffusion Apr. 9, 2002
6355547 Method of forming a self-aligned contact pad for a semiconductor device Mar. 12, 2002
6340612 Method of fabricating body contacted and backgated transistors Jan. 22, 2002
6339005 Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET Jan. 15, 2002
6329291 Method of forming a lower storage node of a capacitor for dynamic random access memory Dec. 11, 2001
6319824 Method of forming a contact hole in a semiconductor device Nov. 20, 2001
6316311 Method of forming borderless contact Nov. 13, 2001
6316348 High selectivity Si-rich SiON etch-stop layer Nov. 13, 2001
6303491 Method for fabricating self-aligned contact hole Oct. 16, 2001
6303418 Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer Oct. 16, 2001
6300178 Semiconductor device with self-aligned contact and manufacturing method thereof Oct. 9, 2001
6300184 Method of manufacturing a CMOS transistor Oct. 9, 2001
6297136 Method for fabricating an embedded semiconductor device Oct. 2, 2001
6287953 Minimizing transistor size in integrated circuits Sep. 11, 2001
6284648 Semiconductor processing method of forming a buried contact Sep. 4, 2001
6281058 Method of forming DRAM circuitry on a semiconductor substrate Aug. 28, 2001
6281064 Method for providing dual work function doping and protective insulating cap Aug. 28, 2001
6277743 Method of fabricating self-aligned silicide Aug. 21, 2001
6274421 Method of making metal gate sub-micron MOS transistor Aug. 14, 2001
6258647 Method of fabricating semiconductor device Jul. 10, 2001
6258616 Method of making a semiconductor device having a non-alloyed ohmic contact to a buried doped layer Jul. 10, 2001
6251711 Method for forming bridge free silicide Jun. 26, 2001
6245608 Ion implantation process for forming contact regions in semiconductor materials Jun. 12, 2001
6221728 Semiconductor device manufacturing method Apr. 24, 2001
6218275 Process for forming self-aligned contact of semiconductor device Apr. 17, 2001
6214658 Self-aligned contact structure and method Apr. 10, 2001
6207514 Method for forming borderless gate structures and apparatus formed thereby Mar. 27, 2001
6194297 Method for forming salicide layers Feb. 27, 2001
6190953 Semiconductor device and method for producing same Feb. 20, 2001
6187675 Method for fabrication of a low resistivity MOSFET gate with thick metal silicide on polysilicon Feb. 13, 2001
6184071 Semiconductor device and method for fabricating the same Feb. 6, 2001
6177304 Self-aligned contact process using a poly-cap mask Jan. 23, 2001
6165826 Transistor with low resistance tip and method of fabrication in a CMOS process Dec. 26, 2000
6159844 Fabrication of gate and diffusion contacts in self-aligned contact process Dec. 12, 2000
6156602 Self-aligned precise high sheet RHO register for mixed-signal application Dec. 5, 2000
6153457 Method of fabricating self-align-contact Nov. 28, 2000
6153485 Salicide formation on narrow poly lines by pulling back of spacer Nov. 28, 2000
6153498 Method of fabricating a buried contact Nov. 28, 2000
6146978 Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance Nov. 14, 2000
6143613 Selective exclusion of silicide formation to make polysilicon resistors Nov. 7, 2000
6143595 Method for forming buried contact Nov. 7, 2000
6140171 FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication Oct. 31, 2000
6136636 Method of manufacturing deep sub-micron CMOS transistors Oct. 24, 2000
6136637 Method of forming CMOS circuitry including patterning conductive material overlying field isolation oxide Oct. 24, 2000

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