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Class Information
Number: 438/226
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Complementary insulated gate field effect transistors (i.e., cmos) > Including isolation structure > Recessed oxide formed by localized oxidation (i.e., locos) > With epitaxial semiconductor layer formation
Description: Process for making complementary insulated gate field effect transistors with dielectric isolation formed by selectively oxidizing semiconductive regions of the substrate combined with a step of forming an epitaxial semiconductor layer.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7615390 |
Method and apparatus for forming expitaxial layers |
Nov. 10, 2009 |
| 7601582 |
Method for manufacturing a semiconductor device having a device isolation trench |
Oct. 13, 2009 |
| 7598142 |
CMOS device with dual-epi channels and self-aligned contacts |
Oct. 6, 2009 |
| 7524707 |
Modified hybrid orientation technology |
Apr. 28, 2009 |
| 7510925 |
Method of manufacturing semiconductor device, and semiconductor device |
Mar. 31, 2009 |
| 7432167 |
Method of fabricating a strained silicon channel metal oxide semiconductor transistor |
Oct. 7, 2008 |
| 7402485 |
Method of forming a semiconductor device |
Jul. 22, 2008 |
| 7402477 |
Method of making a multiple crystal orientation semiconductor device |
Jul. 22, 2008 |
| 7393762 |
Charge-free low-temperature method of forming thin film-based nanoscale materials and structures on a substrate |
Jul. 1, 2008 |
| 7320923 |
SRAM cell |
Jan. 22, 2008 |
| 7145187 |
Substrate independent multiple input bi-directional ESD protection structure |
Dec. 5, 2006 |
| 7029979 |
Methods for manufacturing semiconductor devices |
Apr. 18, 2006 |
| 6881641 |
Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same |
Apr. 19, 2005 |
| 6833589 |
Method for manufacturing field effect transistor |
Dec. 21, 2004 |
| 6815278 |
Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations |
Nov. 9, 2004 |
| 6723618 |
Methods of forming field isolation structures |
Apr. 20, 2004 |
| 6667200 |
Method for forming transistor of semiconductor device |
Dec. 23, 2003 |
| 6657262 |
Monolithically integrated electronic device and fabrication process therefor |
Dec. 2, 2003 |
| 6649481 |
Methods of fabricating a semiconductor device structure for manufacturing high-density and high-performance integrated-circuits |
Nov. 18, 2003 |
| 6627515 |
Method of fabricating a non-floating body device with enhanced performance |
Sep. 30, 2003 |
| 6620671 |
Method of fabricating transistor having a single crystalline gate conductor |
Sep. 16, 2003 |
| 6455377 |
Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) |
Sep. 24, 2002 |
| 6423599 |
Method for fabricating a field effect transistor having dual gates in SOI (semiconductor on insulator) technology |
Jul. 23, 2002 |
| 6413829 |
Field effect transistor in SOI technology with schottky-contact extensions |
Jul. 2, 2002 |
| 6376293 |
Shallow drain extenders for CMOS transistors using replacement gate design |
Apr. 23, 2002 |
| 6368925 |
Method of forming an EPI-channel in a semiconductor device |
Apr. 9, 2002 |
| 6316303 |
Method of fabricating a MOS transistor having SEG silicon |
Nov. 13, 2001 |
| 6303441 |
Semiconductor device and method for fabricating the same |
Oct. 16, 2001 |
| 6287924 |
Integrated circuit and method |
Sep. 11, 2001 |
| 6287969 |
Method of forming a superconductor |
Sep. 11, 2001 |
| 6248620 |
Method for fabricating a field effect-controlled semiconductor component |
Jun. 19, 2001 |
| 6225230 |
Method of manufacturing semiconductor device |
May. 1, 2001 |
| 6165826 |
Transistor with low resistance tip and method of fabrication in a CMOS process |
Dec. 26, 2000 |
| 6162689 |
Multi-depth junction formation tailored to silicide formation |
Dec. 19, 2000 |
| 6159822 |
Self-planarized shallow trench isolation |
Dec. 12, 2000 |
| 6136637 |
Method of forming CMOS circuitry including patterning conductive material overlying field isolation oxide |
Oct. 24, 2000 |
| 6130132 |
Clean process for manufacturing of split-gate flash memory device having floating gate electrode with sharp peak |
Oct. 10, 2000 |
| 6110803 |
Method for fabricating a high-bias device |
Aug. 29, 2000 |
| 6103575 |
Method of forming a single poly cylindrical flash memory cell having high coupling ratio |
Aug. 15, 2000 |
| 6100125 |
LDD structure for ESD protection and method of fabrication |
Aug. 8, 2000 |
| 6043114 |
Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device |
Mar. 28, 2000 |
| 6017785 |
Method for improving latch-up immunity and interwell isolation in a semiconductor device |
Jan. 25, 2000 |
| 6010929 |
Method for forming high voltage and low voltage transistors on the same substrate |
Jan. 4, 2000 |
| 5976925 |
Process of fabricating a semiconductor devise having asymmetrically-doped active region and gate electrode |
Nov. 2, 1999 |
| 5953604 |
Methods for making compact P-channel/N-channel transistor structure |
Sep. 14, 1999 |
| 5885876 |
Methods of fabricating short channel fermi-threshold field effect transistors including drain field termination region |
Mar. 23, 1999 |
| 5854509 |
Method of fabricating semiconductor device and semiconductor device |
Dec. 29, 1998 |
| 5783469 |
Method for making nitrogenated gate structure for improved transistor performance |
Jul. 21, 1998 |
| 5670397 |
Dual poly-gate deep submicron CMOS with buried contact technology |
Sep. 23, 1997 |
| 5624858 |
Method of manufacturing a semiconductor device with increased breakdown voltage |
Apr. 29, 1997 |
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