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Class Information
Number: 438/219
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Complementary insulated gate field effect transistors (i.e., cmos) > Including isolation structure > Total dielectric isolation
Description: Process for making complementary insulated gate field effect transistors in which at least one of the insulated gate complementary field effect transistors is fully electrically isolated by dielectric insulative material from laterally adjacent semiconductive regions.










Patents under this class:
1 2 3

Patent Number Title Of Patent Date Issued
8692266 Circuit substrate structure Apr. 8, 2014
8685830 Method of filling shallow trenches Apr. 1, 2014
8679938 Shallow trench isolation for device including deep trench capacitors Mar. 25, 2014
8642429 Wide and deep oxide trench in a semiconductor substrate with interspersed vertical oxide ribs Feb. 4, 2014
8575694 Insulated gate bipolar transistor structure having low substrate leakage Nov. 5, 2013
8530299 Electronic device including a well region Sep. 10, 2013
8513087 Processes for forming isolation structures for integrated circuit devices Aug. 20, 2013
8497171 FinFET method and structure with embedded underlying anti-punch through layer Jul. 30, 2013
8440581 Systems and methods for non-periodic pulse sequential lateral solidification May. 14, 2013
8431454 Fabricating process of circuit substrate and circuit substrate structure Apr. 30, 2013
8420490 High-performance semiconductor device and method of manufacturing the same Apr. 16, 2013
8404537 Method of manufacturing semiconductor device Mar. 26, 2013
8384188 Semiconductor device and fabrication method thereof Feb. 26, 2013
8361856 Memory cells, arrays of memory cells, and methods of forming memory cells Jan. 29, 2013
8361858 Reduction of thickness variations of a threshold semiconductor alloy by reducing patterning non-uniformities prior to depositing the semiconductor alloy Jan. 29, 2013
8247297 Method of filling large deep trench with high quality oxide for semiconductor devices Aug. 21, 2012
8198171 Semiconductor device and fabrication method thereof Jun. 12, 2012
8105893 Diffusion sidewall for a semiconductor structure Jan. 31, 2012
8097503 Method of manufacturing semiconductor device Jan. 17, 2012
7977198 Semiconductor device and method of manufacturing semiconductor device Jul. 12, 2011
7951683 In-situ process layer using silicon-rich-oxide for etch selectivity in high AR gapfill May. 31, 2011
7939394 Multiple-depth STI trenches in integrated circuit fabrication May. 10, 2011
7906388 Semiconductor device and method for manufacture Mar. 15, 2011
7888197 Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer Feb. 15, 2011
7880261 Isolation technique allowing both very high and low voltage circuits to be fabricated on the same chip Feb. 1, 2011
7858467 Method of manufacturing semiconductor device Dec. 28, 2010
7829407 Method of fabricating a stressed MOSFET by bending SOI region Nov. 9, 2010
7807520 Method for manufacturing semiconductor device Oct. 5, 2010
7741171 Oxygen-rich layers underlying BPSG Jun. 22, 2010
7709317 Method to increase strain enhancement with spacerless FET and dual liner process May. 4, 2010
7659587 Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer Feb. 9, 2010
7645663 Method of producing non volatile memory device Jan. 12, 2010
7642144 Transistors with recessed active trenches for increased effective gate width Jan. 5, 2010
7642151 Semiconductor device and method of manufacturing the same Jan. 5, 2010
7625811 Method for producing distinct first and second active semi-conducting zones and use thereof for fabricating C-MOS structures Dec. 1, 2009
7553741 Manufacturing method of semiconductor device Jun. 30, 2009
7510926 Technique for providing stress sources in MOS transistors in close proximity to a channel region Mar. 31, 2009
7485521 Self-aligned dual stressed layers for NFET and PFET Feb. 3, 2009
7396715 Semiconductor device and manufacturing method of the same Jul. 8, 2008
7279769 Semiconductor device and manufacturing method thereof Oct. 9, 2007
7262486 SOI substrate and method for manufacturing the same Aug. 28, 2007
7253068 Dual SOI film thickness for body resistance control Aug. 7, 2007
7247543 Decoupling capacitor Jul. 24, 2007
7235460 Method of forming active and isolation areas with split active patterning Jun. 26, 2007
7205190 Semiconductor device fabrication method Apr. 17, 2007
7202125 Low-voltage, multiple thin-gate oxide and low-resistance gate electrode Apr. 10, 2007
7189606 Method of forming fully-depleted (FD) SOI MOSFET access transistor Mar. 13, 2007
7172914 Method of making uniform oxide layer Feb. 6, 2007
7135365 Method of manufacturing MOS transistors Nov. 14, 2006
7115463 Patterning SOI with silicon mask to create box at different depths Oct. 3, 2006

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