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Class Information
Number: 438/219
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Complementary insulated gate field effect transistors (i.e., cmos) > Including isolation structure > Total dielectric isolation
Description: Process for making complementary insulated gate field effect transistors in which at least one of the insulated gate complementary field effect transistors is fully electrically isolated by dielectric insulative material from laterally adjacent semiconductive regions.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7625811 |
Method for producing distinct first and second active semi-conducting zones and use thereof for fabricating C-MOS structures |
Dec. 1, 2009 |
| 7553741 |
Manufacturing method of semiconductor device |
Jun. 30, 2009 |
| 7510926 |
Technique for providing stress sources in MOS transistors in close proximity to a channel region |
Mar. 31, 2009 |
| 7485521 |
Self-aligned dual stressed layers for NFET and PFET |
Feb. 3, 2009 |
| 7396715 |
Semiconductor device and manufacturing method of the same |
Jul. 8, 2008 |
| 7279769 |
Semiconductor device and manufacturing method thereof |
Oct. 9, 2007 |
| 7262486 |
SOI substrate and method for manufacturing the same |
Aug. 28, 2007 |
| 7253068 |
Dual SOI film thickness for body resistance control |
Aug. 7, 2007 |
| 7247543 |
Decoupling capacitor |
Jul. 24, 2007 |
| 7235460 |
Method of forming active and isolation areas with split active patterning |
Jun. 26, 2007 |
| 7205190 |
Semiconductor device fabrication method |
Apr. 17, 2007 |
| 7202125 |
Low-voltage, multiple thin-gate oxide and low-resistance gate electrode |
Apr. 10, 2007 |
| 7189606 |
Method of forming fully-depleted (FD) SOI MOSFET access transistor |
Mar. 13, 2007 |
| 7172914 |
Method of making uniform oxide layer |
Feb. 6, 2007 |
| 7135365 |
Method of manufacturing MOS transistors |
Nov. 14, 2006 |
| 7115463 |
Patterning SOI with silicon mask to create box at different depths |
Oct. 3, 2006 |
| 7075149 |
Semiconductor device and its manufacturing method |
Jul. 11, 2006 |
| 7060549 |
SRAM devices utilizing tensile-stressed strain films and methods for fabricating the same |
Jun. 13, 2006 |
| 7052948 |
Film or layer made of semi-conductive material and method for producing said film or layer |
May. 30, 2006 |
| 7053451 |
Semiconductor device having impurity region under isolation region |
May. 30, 2006 |
| 7049677 |
Low cost dielectric isolation method for integration of vertical power MOSFET and lateral driver devices |
May. 23, 2006 |
| 7022565 |
Method of fabricating a trench capacitor of a mixed mode integrated circuit |
Apr. 4, 2006 |
| 7005342 |
Method to fabricate surface p-channel CMOS |
Feb. 28, 2006 |
| 6977204 |
Method for forming contact plug having double doping distribution in semiconductor device |
Dec. 20, 2005 |
| 6964883 |
Bi-directional silicon controlled rectifier for electrostatic discharge protection |
Nov. 15, 2005 |
| 6958266 |
Semiconductor device, method of manufacturing same and method of designing same |
Oct. 25, 2005 |
| 6955957 |
Method of forming a floating gate in a flash memory device |
Oct. 18, 2005 |
| 6921688 |
Method of and apparatus for integrating flash EPROM and SRAM cells on a common substrate |
Jul. 26, 2005 |
| 6900108 |
High temperature sensors utilizing doping controlled, dielectrically isolated beta silicon carbide (SiC) sensing elements on a specifically selected high temperature force collecting membrane |
May. 31, 2005 |
| 6887772 |
Structures of high voltage device and low voltage device, and method of manufacturing the same |
May. 3, 2005 |
| 6876054 |
Integrable DC/AC voltage transformer/isolator and ultra-large-scale circuit incorporating the same |
Apr. 5, 2005 |
| 6867086 |
Multi-step deposition and etch back gap fill process |
Mar. 15, 2005 |
| 6830977 |
METHODS OF FORMING AN ISOLATION TRENCH IN A SEMICONDUCTOR, METHODS OF FORMING AN ISOLATION TRENCH IN A SURFACE OF A SILICON WAFER, METHODS OF FORMING AN ISOLATION TRENCH-ISOLATED TRANSISTOR, T |
Dec. 14, 2004 |
| 6809014 |
Method to fabricate surface p-channel CMOS |
Oct. 26, 2004 |
| 6777770 |
Films deposited at glancing incidence for multilevel metallization |
Aug. 17, 2004 |
| 6777772 |
Semiconductor device having improved trench structure |
Aug. 17, 2004 |
| 6767781 |
Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask |
Jul. 27, 2004 |
| 6764921 |
Semiconductor device and method for fabricating the same |
Jul. 20, 2004 |
| 6764892 |
Device and method of low voltage SCR protection for high voltage failsafe ESD applications |
Jul. 20, 2004 |
| 6750116 |
Method for fabricating asymmetric inner structure in contacts or trenches |
Jun. 15, 2004 |
| 6734524 |
Electronic component and method of manufacturing same |
May. 11, 2004 |
| 6716691 |
Self-aligned shallow trench isolation process having improved polysilicon gate thickness control |
Apr. 6, 2004 |
| 6706580 |
Semiconductor memory of good retention and its manufacture |
Mar. 16, 2004 |
| 6639296 |
Semiconductor device and method of manufacturing the same |
Oct. 28, 2003 |
| 6633073 |
Method and apparatus for isolating circuits using deep substrate n-well |
Oct. 14, 2003 |
| 6603174 |
Semiconductor device and manufacturing method thereof |
Aug. 5, 2003 |
| 6576959 |
Device and method of low voltage SCR protection for high voltage failsafe ESD applications |
Jun. 10, 2003 |
| 6569729 |
Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application |
May. 27, 2003 |
| 6566223 |
High voltage integrated switching devices on a bonded and trenched silicon substrate |
May. 20, 2003 |
| 6562694 |
Method of manufacturing a semiconductor device comprising semiconductor elements formed in a toplayer of a silicon wafer situated on a buried insulating layer |
May. 13, 2003 |
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