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Class Information
Number: 438/216
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Complementary insulated gate field effect transistors (i.e., cmos) > Gate insulator structure constructed of diverse dielectrics (e.g., mnos, etc.) or of nonsilicon compound
Description: Process for making complementary insulated gate field effect transistors wherein the gate dielectric insulator of at least one of the transistors is constructed of plural diverse dielectrics (e.g., nitride and oxide layers, etc.) or of a nonsilicon containing dielectric compound.

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14

Patent Number Title Of Patent Date Issued
5795821 Process for improving the interface union among dielectric materials in an integrated circuit manufacture Aug. 18, 1998
5770490 Method for producing dual work function CMOS device Jun. 23, 1998
5770492 Self-aligned twin well process Jun. 23, 1998
5763302 Self-aligned twin well process Jun. 9, 1998
5700728 Method of forming an MNOS/MONOS by employing large tilt angle ion implantation underneath the field oxide Dec. 23, 1997
5214298 Complementary heterostructure field effect transistors May. 25, 1993
4849366 Method of making a gated isolated structure Jul. 18, 1989
4454648 Method of making integrated MNOS and CMOS devices in a bulk silicon wafer Jun. 19, 1984

1 2 3 4 5 6 7 8 9 10 11 12 13 14

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