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Class Information
Number: 438/213
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Complementary insulated gate field effect transistors (i.e., cmos) > Common active region
Description: Process for making complementary insulated gate field effect transistors wherein the transistors share a device active region.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8659092 Complementary metal oxide semiconductor transistor and fabricating method thereof Feb. 25, 2014
8597994 Semiconductor device and method of fabrication Dec. 3, 2013
8592872 Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposi Nov. 26, 2013
8513739 Metal-gate high-k reference structure Aug. 20, 2013
8455313 Method for fabricating finFET with merged fins and vertical silicide Jun. 4, 2013
8426298 CMOS devices with Schottky source and drain regions Apr. 23, 2013
8378392 Trench MOSFET with body region having concave-arc shape Feb. 19, 2013
8318523 Thin film transistor, method of fabricating the same and organic light emitting diode display device having the same Nov. 27, 2012
8304306 Fabrication of devices having different interfacial oxide thickness via lateral oxidation Nov. 6, 2012
8114741 Oxygen-rich layers underlying BPSG Feb. 14, 2012
8105892 Thermal dual gate oxide device integration Jan. 31, 2012
8093111 Semiconductor device including partial silicon on insulator fin structure and method for fabricating the same Jan. 10, 2012
8067280 High performance CMOS devices and methods for making same Nov. 29, 2011
7951678 Metal-gate high-k reference structure May. 31, 2011
7919377 Contactless flash memory array Apr. 5, 2011
7871879 Method of manufacturing semiconductor memory device Jan. 18, 2011
7851790 Isolated Germanium nanowire on Silicon fin Dec. 14, 2010
7803684 Method of fabricating semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer Sep. 28, 2010
RE41477 Semiconductor device with a reduced mask count buried layer Aug. 10, 2010
7718481 Semiconductor structure and method of manufacture May. 18, 2010
7704837 Cell based integrated circuit and unit cell architecture therefor Apr. 27, 2010
7675103 Spin transistor using ferromagnet Mar. 9, 2010
7659157 Dual metal gate finFETs with single or dual high-K gate dielectric Feb. 9, 2010
7605447 Highly manufacturable SRAM cells in substrates with hybrid crystal orientation Oct. 20, 2009
7537980 Method of manufacturing a stacked semiconductor device May. 26, 2009
7498253 Local interconnection method and structure for use in semiconductor device Mar. 3, 2009
7462532 Method of fabricating high voltage metal oxide semiconductor device Dec. 9, 2008
7422945 Cell based integrated circuit and unit cell architecture therefor Sep. 9, 2008
7300837 FinFET transistor device on SOI and method of fabrication Nov. 27, 2007
7291882 Programmable and erasable digital switch device and fabrication method and operating method thereof Nov. 6, 2007
7276742 Compound semiconductor light emitting device and its manufacturing method Oct. 2, 2007
7256422 EL display device and electronic device Aug. 14, 2007
7223646 Manufacturing method of semiconductor device suppressing short-channel effect May. 29, 2007
7180158 Semiconductor device and method of manufacture Feb. 20, 2007
7132316 After deposition method of thinning film to reduce pinhole defects Nov. 7, 2006
7115460 Standard cell back bias architecture Oct. 3, 2006
7095092 Semiconductor device and method of forming the same Aug. 22, 2006
7083739 Transfer body and method using the same Aug. 1, 2006
7045409 Semiconductor device having active regions connected together by interconnect layer and method of manufacture thereof May. 16, 2006
6989302 Method for fabricating a p-type shallow junction using diatomic arsenic Jan. 24, 2006
6943407 Low leakage heterojunction vertical transistors and high performance devices thereof Sep. 13, 2005
6908805 Method of manufacturing dual gate oxide film Jun. 21, 2005
6905931 Cell based integrated circuit and unit cell architecture therefor Jun. 14, 2005
6893925 Layout to minimize gate orientation related skew effects May. 17, 2005
6831329 Quick punch through IGBT having gate-controllable DI/DT and reduced EMI during inductive turn off Dec. 14, 2004
6808971 High performance three-dimensional TFT-based CMOS inverters, and computer systems utilizing such novel CMOS inverters Oct. 26, 2004
6720214 Method for manufacturing semiconductor integrated circuit Apr. 13, 2004
6703685 Super self-aligned collector device for mono-and hetero bipolar junction transistors Mar. 9, 2004
6656780 Method of manufacturing a semiconductor device having nitrogen ions by twice RTA processes Dec. 2, 2003
6624497 Semiconductor device with a reduced mask count buried layer Sep. 23, 2003

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