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Class Information
Number: 438/208
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Complementary insulated gate field effect transistors (i.e., cmos) > And additional electrical device > Including bipolar transistor (i.e., bicmos) > Including isolation structure > Isolation by pn junction only
Description: Process for making complementary insulated gate field effect transistors combined with a bipolar transistor in which the transistors are electrically isolated solely through the use of properly biased PN junctions.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7173316 |
Semiconductor device |
Feb. 6, 2007 |
| 7015084 |
Method of manufacturing a field effect transistor and a liquid crystal display using the same |
Mar. 21, 2006 |
| 6974999 |
Semiconductor device and method of manufacturing the same |
Dec. 13, 2005 |
| 6943072 |
Adjustable threshold isolation transistor |
Sep. 13, 2005 |
| 6841437 |
Method of forming a vertical power semiconductor device and structure therefor |
Jan. 11, 2005 |
| 6787880 |
ESD parasitic bipolar transistors with high resistivity regions in the collector |
Sep. 7, 2004 |
| 6784043 |
Methods for forming aligned fuses disposed in an integrated circuit |
Aug. 31, 2004 |
| 6781206 |
Semiconductor device with structure restricting flow of unnecessary current therein |
Aug. 24, 2004 |
| 6653182 |
Process for forming deep and shallow insulative regions of an integrated circuit |
Nov. 25, 2003 |
| 6630377 |
Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process |
Oct. 7, 2003 |
| 6624497 |
Semiconductor device with a reduced mask count buried layer |
Sep. 23, 2003 |
| 6589833 |
ESD parasitic bipolar transistors with high resistivity regions in the collector |
Jul. 8, 2003 |
| 6582997 |
ESD protection scheme for outputs with resistor loading |
Jun. 24, 2003 |
| 6541325 |
Method for fabricating a capacitor device with BiCMOS process and the capacitor device formed thereby |
Apr. 1, 2003 |
| 6521493 |
Semiconductor device with STI sidewall implant |
Feb. 18, 2003 |
| 6472712 |
Semiconductor device with reduced transistor leakage current |
Oct. 29, 2002 |
| 6362036 |
VDMOS transistor protected against over-voltages between source and gate |
Mar. 26, 2002 |
| 6201293 |
Electro optical devices with reduced filter thinning on the edge pixel photosites and method of producing same |
Mar. 13, 2001 |
| 6051457 |
Method for fabricating electrostatic discharge protection device |
Apr. 18, 2000 |
| 6010926 |
Method for forming multiple or modulated wells of semiconductor device |
Jan. 4, 2000 |
| 5899714 |
Fabrication of semiconductor structure having two levels of buried regions |
May. 4, 1999 |
| 5880002 |
Method for making isolated vertical PNP transistor in a digital BiCMOS process |
Mar. 9, 1999 |
| 5856218 |
Bipolar transistor formed by a high energy ion implantation method |
Jan. 5, 1999 |
| 5776807 |
Method for fabricating a triple well for bicmos devices |
Jul. 7, 1998 |
| 5702959 |
Method for making an isolated vertical transistor |
Dec. 30, 1997 |
| 5591657 |
Semiconductor apparatus manufacturing method employing gate side wall self-aligning for masking |
Jan. 7, 1997 |
| 5580798 |
Method of fabricating bipolar transistor having a guard ring |
Dec. 3, 1996 |
| 5556796 |
Self-alignment technique for forming junction isolation and wells |
Sep. 17, 1996 |
| 5470766 |
Efficient method for fabricating optimal BiCMOS N-wells for bipolar and field effect transistors |
Nov. 28, 1995 |
| 5371023 |
Gate circuit, semiconductor integrated circuit device and method of fabrication thereof, semiconductor memory and microprocessor |
Dec. 6, 1994 |
| 5290714 |
Method of forming semiconductor device including a CMOS structure having double-doped channel regions |
Mar. 1, 1994 |
| 5268312 |
Method of forming isolated wells in the fabrication of BiCMOS devices |
Dec. 7, 1993 |
| 5262345 |
Complimentary bipolar/CMOS fabrication method |
Nov. 16, 1993 |
| 5256582 |
Method of forming complementary bipolar and MOS transistor having power and logic structures on the same integrated circuit substrate |
Oct. 26, 1993 |
| 5225365 |
Method of making a substantially planar semiconductor surface |
Jul. 6, 1993 |
| 5208171 |
Process for preparing BiCMOS semiconductor device |
May. 4, 1993 |
| 5156984 |
Manufacturing method for a Bi-CMOS by trenching |
Oct. 20, 1992 |
| 5104829 |
Method of manufacturing semiconductor integrated circuit |
Apr. 14, 1992 |
| 5087579 |
Method for fabricating an integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias |
Feb. 11, 1992 |
| 5070031 |
Complementary semiconductor region fabrication |
Dec. 3, 1991 |
| 4931406 |
Method for manufacturing semiconductor devices having twin wells |
Jun. 5, 1990 |
| 4921811 |
Semiconductor integrated circuit device and a method for manufacturing the same |
May. 1, 1990 |
| 4912054 |
Integrated bipolar-CMOS circuit isolation process for providing different backgate and substrate bias |
Mar. 27, 1990 |
| 4892836 |
Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices |
Jan. 9, 1990 |
| 4806499 |
Method of manufacturing Bi-CMOS semiconductor IC devices using dopant rediffusion |
Feb. 21, 1989 |
| 4769337 |
Method of forming selective polysilicon wiring layer to source, drain and emitter regions by implantation through polysilicon layer |
Sep. 6, 1988 |
| 4724221 |
High-speed, low-power-dissipation integrated circuits |
Feb. 9, 1988 |
| 4694562 |
Method for manufacturing a semiconductor integrated device including bipolar and CMOS transistors |
Sep. 22, 1987 |
| 4637125 |
Method for making a semiconductor integrated device including bipolar transistor and CMOS transistor |
Jan. 20, 1987 |
| 4346512 |
Integrated circuit manufacturing method |
Aug. 31, 1982 |
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