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Class Information
Number: 438/208
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Complementary insulated gate field effect transistors (i.e., cmos) > And additional electrical device > Including bipolar transistor (i.e., bicmos) > Including isolation structure > Isolation by pn junction only
Description: Process for making complementary insulated gate field effect transistors combined with a bipolar transistor in which the transistors are electrically isolated solely through the use of properly biased PN junctions.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8664741 High voltage resistor with pin diode isolation Mar. 4, 2014
8530298 Radiation hardened integrated circuit Sep. 10, 2013
8481381 Superior integrity of high-k metal gate stacks by preserving a resist material above end caps of gate electrode structures Jul. 9, 2013
8338863 Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance Dec. 25, 2012
8299532 ESD protection device structure Oct. 30, 2012
8263472 Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices Sep. 11, 2012
8232156 Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance Jul. 31, 2012
8232158 Compensated isolated p-well DENMOS devices Jul. 31, 2012
8049278 ESD protection for high voltage applications Nov. 1, 2011
7998815 Shallow trench isolation Aug. 16, 2011
7977198 Semiconductor device and method of manufacturing semiconductor device Jul. 12, 2011
7960796 Semiconductor device having element isolation region Jun. 14, 2011
7956432 Photodiode for multiple wavelength operation Jun. 7, 2011
7939397 Method of manufacturing semiconductor device May. 10, 2011
7872325 Reduced-crosstalk wirebonding in an optical communication system Jan. 18, 2011
RE41477 Semiconductor device with a reduced mask count buried layer Aug. 10, 2010
7719080 Semiconductor device with a conduction enhancement layer May. 18, 2010
7642154 BiCMOS device and method of manufacturing a biCMOS device Jan. 5, 2010
7638385 Method of forming a semiconductor device and structure therefor Dec. 29, 2009
7485486 Photodiode for multiple wavelength operation Feb. 3, 2009
7462530 Method for manufacturing a semiconductor device having an element isolation region Dec. 9, 2008
7173316 Semiconductor device Feb. 6, 2007
7015084 Method of manufacturing a field effect transistor and a liquid crystal display using the same Mar. 21, 2006
6974999 Semiconductor device and method of manufacturing the same Dec. 13, 2005
6943072 Adjustable threshold isolation transistor Sep. 13, 2005
6841437 Method of forming a vertical power semiconductor device and structure therefor Jan. 11, 2005
6787880 ESD parasitic bipolar transistors with high resistivity regions in the collector Sep. 7, 2004
6784043 Methods for forming aligned fuses disposed in an integrated circuit Aug. 31, 2004
6781206 Semiconductor device with structure restricting flow of unnecessary current therein Aug. 24, 2004
6653182 Process for forming deep and shallow insulative regions of an integrated circuit Nov. 25, 2003
6630377 Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process Oct. 7, 2003
6624497 Semiconductor device with a reduced mask count buried layer Sep. 23, 2003
6589833 ESD parasitic bipolar transistors with high resistivity regions in the collector Jul. 8, 2003
6582997 ESD protection scheme for outputs with resistor loading Jun. 24, 2003
6541325 Method for fabricating a capacitor device with BiCMOS process and the capacitor device formed thereby Apr. 1, 2003
6521493 Semiconductor device with STI sidewall implant Feb. 18, 2003
6472712 Semiconductor device with reduced transistor leakage current Oct. 29, 2002
6362036 VDMOS transistor protected against over-voltages between source and gate Mar. 26, 2002
6201293 Electro optical devices with reduced filter thinning on the edge pixel photosites and method of producing same Mar. 13, 2001
6051457 Method for fabricating electrostatic discharge protection device Apr. 18, 2000
6010926 Method for forming multiple or modulated wells of semiconductor device Jan. 4, 2000
5899714 Fabrication of semiconductor structure having two levels of buried regions May. 4, 1999
5880002 Method for making isolated vertical PNP transistor in a digital BiCMOS process Mar. 9, 1999
5856218 Bipolar transistor formed by a high energy ion implantation method Jan. 5, 1999
5776807 Method for fabricating a triple well for bicmos devices Jul. 7, 1998
5702959 Method for making an isolated vertical transistor Dec. 30, 1997
5591657 Semiconductor apparatus manufacturing method employing gate side wall self-aligning for masking Jan. 7, 1997
5580798 Method of fabricating bipolar transistor having a guard ring Dec. 3, 1996
5556796 Self-alignment technique for forming junction isolation and wells Sep. 17, 1996
5470766 Efficient method for fabricating optimal BiCMOS N-wells for bipolar and field effect transistors Nov. 28, 1995

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