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Class Information
Number: 438/204
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Complementary insulated gate field effect transistors (i.e., cmos) > And additional electrical device > Including bipolar transistor (i.e., bicmos) > Lateral bipolar transistor
Description: Process for making complementary insulated gate field effect transistors additionally having a bipolar transistor possessing a horizontal-type structure so that current flow between its emitter and collector regions is parallel to a major surface of the semiconductor substrate.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7381606 |
Semiconductor device and method of forming a semiconductor device |
Jun. 3, 2008 |
| 7364960 |
Methods for fabricating solid state image sensor devices having non-planar transistors |
Apr. 29, 2008 |
| 7358573 |
Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same |
Apr. 15, 2008 |
| 7344935 |
Method of manufacturing a semiconductor integrated circuit device |
Mar. 18, 2008 |
| 7285454 |
Bipolar transistors with low base resistance for CMOS integrated circuits |
Oct. 23, 2007 |
| 7217609 |
Semiconductor fabrication process, lateral PNP transistor, and integrated circuit |
May. 15, 2007 |
| 7214558 |
Method for forming patterns on a semiconductor device using a lift off technique |
May. 8, 2007 |
| 7163856 |
Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor |
Jan. 16, 2007 |
| 7132344 |
Super self-aligned BJT with base shorted field plate and method of fabricating |
Nov. 7, 2006 |
| 7115460 |
Standard cell back bias architecture |
Oct. 3, 2006 |
| 7029938 |
Method for forming patterns on a semiconductor device using a lift off technique |
Apr. 18, 2006 |
| 7001806 |
Semiconductor structure with increased breakdown voltage and method for producing the semiconductor structure |
Feb. 21, 2006 |
| 6987039 |
Forming lateral bipolar junction transistor in CMOS flow |
Jan. 17, 2006 |
| 6875648 |
Fabrication of an EEPROM cell with emitter-polysilicon source/drain regions |
Apr. 5, 2005 |
| 6815282 |
Silicon on insulator field effect transistor having shared body contact |
Nov. 9, 2004 |
| 6794237 |
Lateral heterojunction bipolar transistor |
Sep. 21, 2004 |
| 6784065 |
Bipolar transistor with ultra small self-aligned polysilicon emitter and method of forming the transistor |
Aug. 31, 2004 |
| 6767779 |
Asymmetrical MOSFET layout for high currents and high speed operation |
Jul. 27, 2004 |
| 6750109 |
Halo-free non-rectifying contact on chip with halo source/drain diffusion |
Jun. 15, 2004 |
| 6692994 |
Method for manufacturing a programmable chalcogenide fuse within a semiconductor device |
Feb. 17, 2004 |
| 6667202 |
Semiconductor device and method for making the same |
Dec. 23, 2003 |
| 6638824 |
Metal gate double diffusion MOSFET with improved switching speed and reduced gate tunnel leakage |
Oct. 28, 2003 |
| 6616786 |
Process for applying an ink-only label to a polymeric surface |
Sep. 9, 2003 |
| 6570240 |
Semiconductor device having a lateral bipolar transistor and method of manufacturing same |
May. 27, 2003 |
| 6551869 |
Lateral PNP and method of manufacture |
Apr. 22, 2003 |
| 6528374 |
Method for forming dielectric stack without interfacial layer |
Mar. 4, 2003 |
| 6495407 |
Method of making an article comprising an oxide layer on a GaAs-based semiconductor body |
Dec. 17, 2002 |
| 6475848 |
Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor |
Nov. 5, 2002 |
| 6468825 |
Method for producing semiconductor temperature sensor |
Oct. 22, 2002 |
| 6440788 |
Implant sequence for multi-function semiconductor structure and method |
Aug. 27, 2002 |
| 6410377 |
Method for integrating CMOS sensor and high voltage device |
Jun. 25, 2002 |
| 6372595 |
Lateral bipolar junction transistor with reduced parasitic current loss |
Apr. 16, 2002 |
| 6365448 |
Structure and method for gated lateral bipolar transistors |
Apr. 2, 2002 |
| 6362034 |
Method of forming MOSFET gate electrodes having reduced depletion region growth sensitivity to applied electric field |
Mar. 26, 2002 |
| 6326253 |
Method for fabricating semiconductor device including MIS and bipolar transistors |
Dec. 4, 2001 |
| 6300669 |
Semiconductor integrated circuit device and method of designing same |
Oct. 9, 2001 |
| 6281060 |
Method of manufacturing a semiconductor device containing a BiCMOS circuit |
Aug. 28, 2001 |
| 6271069 |
Method of making an article comprising an oxide layer on a GaAs-based semiconductor body |
Aug. 7, 2001 |
| 6249031 |
High gain lateral PNP and NPN bipolar transistor and process compatible with CMOS for making BiCMOS circuits |
Jun. 19, 2001 |
| 6245609 |
High voltage transistor using P+ buried layer |
Jun. 12, 2001 |
| 6174779 |
Method for manufacturing a lateral bipolar transistor |
Jan. 16, 2001 |
| 6127236 |
Method of forming a lateral bipolar transistor |
Oct. 3, 2000 |
| 6117718 |
Method for forming BJT via formulation of high voltage device in ULSI |
Sep. 12, 2000 |
| 6093613 |
Method for making high gain lateral PNP and NPN bipolar transistor compatible with CMOS for making BICMOS circuits |
Jul. 25, 2000 |
| 6051456 |
Semiconductor component and method of manufacture |
Apr. 18, 2000 |
| 6037630 |
Semiconductor device with gate electrode portion and method of manufacturing the same |
Mar. 14, 2000 |
| 5953600 |
Fabrication of bipolar/CMOS integrated circuits |
Sep. 14, 1999 |
| 5869366 |
Method for forming voltage clamp having a breakdown voltage of 40 Vdc |
Feb. 9, 1999 |
| 5846858 |
SOI-BiCMOS method |
Dec. 8, 1998 |
| 5773338 |
Bipolar transistor with MOS-controlled protection for reverse-biased emitter-based junction |
Jun. 30, 1998 |
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