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Class Information
Number: 438/203
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having insulated gate (e.g., igfet, misfet, mosfet, etc.) > Complementary insulated gate field effect transistors (i.e., cmos) > And additional electrical device > Including bipolar transistor (i.e., bicmos) > Complementary bipolar transistors
Description: Process for making complementary insulated gate field effect transistors combined with a first bipolar transistor which additionally contains a second bipolar transistor which is of opposite conductivity type to the first bipolar transistor.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 6987039 |
Forming lateral bipolar junction transistor in CMOS flow |
Jan. 17, 2006 |
| 6933201 |
Method for manufacturing semiconductor device |
Aug. 23, 2005 |
| 6858486 |
Vertical bipolar transistor formed using CMOS processes |
Feb. 22, 2005 |
| 6849492 |
Method for forming standard voltage threshold and low voltage threshold MOSFET devices |
Feb. 1, 2005 |
| 6830967 |
Method for forming CMOS transistor spacers in a BiCMOS process |
Dec. 14, 2004 |
| 6767797 |
Method of fabricating complementary self-aligned bipolar transistors |
Jul. 27, 2004 |
| 6730557 |
Semiconductor device and production thereof |
May. 4, 2004 |
| 6706567 |
High voltage device having polysilicon region in trench and fabricating method thereof |
Mar. 16, 2004 |
| 6673703 |
Method of fabricating an integrated circuit |
Jan. 6, 2004 |
| 6670229 |
Bipolar transistor produced using processes compatible with those employed in the manufacture of MOS device |
Dec. 30, 2003 |
| 6667202 |
Semiconductor device and method for making the same |
Dec. 23, 2003 |
| 6657268 |
Metal gate stack with etch stop layer having implanted metal species |
Dec. 2, 2003 |
| 6610565 |
Method of forming a CMOS type semiconductor device |
Aug. 26, 2003 |
| 6590273 |
Semiconductor integrated circuit device and manufacturing method thereof |
Jul. 8, 2003 |
| 6576535 |
Carbon doped epitaxial layer for high speed CB-CMOS |
Jun. 10, 2003 |
| 6569730 |
High voltage transistor using P+ buried layer |
May. 27, 2003 |
| 6566217 |
Manufacturing process for semiconductor device |
May. 20, 2003 |
| 6541824 |
Modified source side inserted anti-type diffusion ESD protection device |
Apr. 1, 2003 |
| 6531368 |
Method of fabricating a semiconductor device having a metal oxide high-k gate insulator by localized laser irradiation and a device thereby formed |
Mar. 11, 2003 |
| 6475850 |
Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits |
Nov. 5, 2002 |
| 6472288 |
Method of fabricating bipolar transistors with independent impurity profile on the same chip |
Oct. 29, 2002 |
| 6465822 |
Semiconductor device having a reduced-capacitance conductive layer and fabrication method for the same |
Oct. 15, 2002 |
| 6444512 |
Dual metal gate transistors for CMOS process |
Sep. 3, 2002 |
| 6440787 |
Manufacturing method of semiconductor device |
Aug. 27, 2002 |
| 6396100 |
Efficient fabrication process for dual well type structures |
May. 28, 2002 |
| 6383855 |
High speed, low cost BICMOS process using profile engineering |
May. 7, 2002 |
| 6365447 |
High-voltage complementary bipolar and BiCMOS technology using double expitaxial growth |
Apr. 2, 2002 |
| 6362031 |
Semiconductor TFT, producing method thereof, semiconductor TFT array substrate and liquid crystal display using the same |
Mar. 26, 2002 |
| 6352887 |
Merged bipolar and CMOS circuit and method |
Mar. 5, 2002 |
| 6333237 |
Method for manufacturing a semiconductor device |
Dec. 25, 2001 |
| 6323075 |
Method of fabricating semiconductor device |
Nov. 27, 2001 |
| 6316301 |
Method for sizing PMOS pull-up devices |
Nov. 13, 2001 |
| 6306695 |
Modified source side inserted anti-type diffusion ESD protection device |
Oct. 23, 2001 |
| 6300669 |
Semiconductor integrated circuit device and method of designing same |
Oct. 9, 2001 |
| 6291282 |
Method of forming dual metal gate structures or CMOS devices |
Sep. 18, 2001 |
| 6271068 |
Method for making improved polysilicon emitters for bipolar transistors on BiCMOS integrated circuits |
Aug. 7, 2001 |
| 6268250 |
Efficient fabrication process for dual well type structures |
Jul. 31, 2001 |
| 6245609 |
High voltage transistor using P+ buried layer |
Jun. 12, 2001 |
| 6245604 |
Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits |
Jun. 12, 2001 |
| 6235588 |
Method of manufacturing a memory point in BICMOS technology |
May. 22, 2001 |
| 6177298 |
Electrostatic discharge protection circuit for an integrated circuit and method of manufacturing |
Jan. 23, 2001 |
| 6140170 |
Manufacture of complementary MOS and bipolar integrated circuits |
Oct. 31, 2000 |
| 6137147 |
Bipolar transistor and semiconductor integrated circuit device |
Oct. 24, 2000 |
| 6117718 |
Method for forming BJT via formulation of high voltage device in ULSI |
Sep. 12, 2000 |
| 6093595 |
Method of forming source and drain regions in complementary MOS transistors |
Jul. 25, 2000 |
| 6090652 |
Method of manufacturing a semiconductor device including implanting threshold voltage adjustment ions |
Jul. 18, 2000 |
| 6077736 |
Method of fabricating a semiconductor device |
Jun. 20, 2000 |
| 6071767 |
High performance/high density BICMOS process |
Jun. 6, 2000 |
| 6030864 |
Vertical NPN transistor for 0.35 micrometer node CMOS logic technology |
Feb. 29, 2000 |
| RE36441 |
Semiconductor device and a method of manufacturing same |
Dec. 14, 1999 |
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