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Class Information
Number: 438/194
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having junction gate (e.g., jfet, sit, etc.) > Doping of semiconductive channel region beneath gate (e.g., threshold voltage adjustment, etc.)
Description: Process for making a junction gate field effect transistor having a step of introducing an electrically active dopant species into the semiconductor channel region beneath the gate electrode.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7622356 |
Method of fabricating metal oxide semiconductor field effect transistor |
Nov. 24, 2009 |
| 7615802 |
Semiconductor structure comprising a highly doped conductive channel region and method for producing a semiconductor structure |
Nov. 10, 2009 |
| 7569873 |
Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys |
Aug. 4, 2009 |
| 7566600 |
SOI device with reduced drain induced barrier lowering |
Jul. 28, 2009 |
| 7528026 |
Method for reducing silicide defects by removing contaminants prior to drain/source activation |
May. 5, 2009 |
| 7501317 |
Method of manufacturing semiconductor device |
Mar. 10, 2009 |
| 7470972 |
Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress |
Dec. 30, 2008 |
| 7411231 |
JFET with drain and/or source modification implant |
Aug. 12, 2008 |
| 7341901 |
Semiconductor processing methods of forming integrated circuitry |
Mar. 11, 2008 |
| 7335988 |
Use of palladium in IC manufacturing with conductive polymer bump |
Feb. 26, 2008 |
| 7297580 |
Methods of fabricating transistors having buried p-type layers beneath the source region |
Nov. 20, 2007 |
| 7265006 |
Method of fabricating heterojunction devices integrated with CMOS |
Sep. 4, 2007 |
| 7226824 |
Nitrogen controlled growth of dislocation loop in stress enhanced transistor |
Jun. 5, 2007 |
| 7195968 |
Method of fabricating semiconductor device |
Mar. 27, 2007 |
| 7166506 |
Poly open polish process |
Jan. 23, 2007 |
| 7135416 |
Method of manufacturing semiconductor device |
Nov. 14, 2006 |
| 7122411 |
SOI device with reduced drain induced barrier lowering |
Oct. 17, 2006 |
| 7118948 |
Semiconductor wafer having different impurity concentrations in respective regions |
Oct. 10, 2006 |
| 7067363 |
Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances |
Jun. 27, 2006 |
| 7067362 |
Integrated circuit with protected implantation profiles and method for the formation thereof |
Jun. 27, 2006 |
| 7060576 |
Epitaxially deposited source/drain |
Jun. 13, 2006 |
| 7045405 |
Semiconductor processing methods of forming integrated circuitry |
May. 16, 2006 |
| 7022560 |
Method to manufacture high voltage MOS transistor by ion implantation |
Apr. 4, 2006 |
| 6924180 |
Method of forming a pocket implant region after formation of composite insulator spacers |
Aug. 2, 2005 |
| 6919241 |
Superjunction device and process for its manufacture |
Jul. 19, 2005 |
| 6887735 |
Photodetector and device employing the photodetector for converting an optical signal into an electrical signal |
May. 3, 2005 |
| 6875646 |
Semiconductor processing methods of forming integrated circuitry |
Apr. 5, 2005 |
| 6872609 |
Narrow bitline using Safier for mirrorbit |
Mar. 29, 2005 |
| 6861322 |
Method of manufacturing a semiconductor device |
Mar. 1, 2005 |
| 6767772 |
Active matrix substrate, electrooptical device, and method of producing active matrix substrate |
Jul. 27, 2004 |
| 6759288 |
Double LDD devices for improved DRAM refresh |
Jul. 6, 2004 |
| 6720222 |
Method of manufacturing semiconductor device |
Apr. 13, 2004 |
| 6599782 |
Semiconductor device and method of fabricating thereof |
Jul. 29, 2003 |
| 6579751 |
Semiconductor processing methods of forming integrated circuitry |
Jun. 17, 2003 |
| 6555850 |
Field-effect transistor |
Apr. 29, 2003 |
| 6551865 |
Silicon carbide semiconductor device and method of fabricating the same |
Apr. 22, 2003 |
| 6541825 |
Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same |
Apr. 1, 2003 |
| 6486011 |
JFET structure and manufacture method for low on-resistance and low voltage application |
Nov. 26, 2002 |
| 6455362 |
Double LDD devices for improved dram refresh |
Sep. 24, 2002 |
| 6417550 |
High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage |
Jul. 9, 2002 |
| 6380012 |
Boron difluoride plasma doping method for forming ultra-shallow junction |
Apr. 30, 2002 |
| 6355513 |
Asymmetric depletion region for normally off JFET |
Mar. 12, 2002 |
| 6316303 |
Method of fabricating a MOS transistor having SEG silicon |
Nov. 13, 2001 |
| 6274415 |
Self-aligned Vt implant |
Aug. 14, 2001 |
| 6251716 |
JFET structure and manufacture method for low on-resistance and low voltage application |
Jun. 26, 2001 |
| 6238982 |
Multiple threshold voltage semiconductor device fabrication technology |
May. 29, 2001 |
| 6198116 |
Complementary heterostructure integrated single metal transistor fabrication method |
Mar. 6, 2001 |
| 6194760 |
Double-diffused MOS transistor and method of fabricating the same |
Feb. 27, 2001 |
| 6180464 |
Metal oxide semiconductor device with localized laterally doped channel |
Jan. 30, 2001 |
| 6177303 |
Method of manufacturing a semiconductor device with a field effect transistor |
Jan. 23, 2001 |
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