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Class Information
Number: 438/193
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having junction gate (e.g., jfet, sit, etc.) > Vertical channel > Multiple parallel current paths (e.g., grid gate, etc.)
Description: Process for making a junction gate field effect transistor wherein the junction gate which controls the vertical channel consists of a plurality of parallel current paths.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8679950 Manufacturing method for semiconductor device having side by side different fins Mar. 25, 2014
8642463 Routing layer for mitigating stress in a semiconductor die Feb. 4, 2014
8580584 System and method for increasing productivity of organic light emitting diode material screening Nov. 12, 2013
8513125 Manufacturing a microelectronic device comprising silicon and germanium nanowires integrated on a same substrate Aug. 20, 2013
8492228 Field effect transistor devices having thick gate dielectric layers and thin gate dielectric layers Jul. 23, 2013
8482028 Semiconductor device Jul. 9, 2013
8389973 Memory using tunneling field effect transistors Mar. 5, 2013
8349676 Electrostatic discharge management apparatus, systems, and methods Jan. 8, 2013
8343836 Recessed gate channel with low Vt corner Jan. 1, 2013
8298837 System and method for increasing productivity of organic light emitting diode material screening Oct. 30, 2012
8101486 Methods for forming isolated fin structures on bulk semiconductor material Jan. 24, 2012
7927938 Fin-JFET Apr. 19, 2011
7858429 Packaged microelectronic imagers and methods of packaging microelectronic imagers Dec. 28, 2010
7851832 Semiconductor device Dec. 14, 2010
7851283 Field effect transistor with raised source/drain fin straps Dec. 14, 2010
7718480 ESD clamps and NMOS arrays with increased electrical overstress robustness May. 18, 2010
7638379 Vertical-channel junction field-effect transistors having buried gates and methods of making Dec. 29, 2009
7615802 Semiconductor structure comprising a highly doped conductive channel region and method for producing a semiconductor structure Nov. 10, 2009
7504677 Multi-gate enhancement mode RF switch and bias arrangement Mar. 17, 2009
7501297 Thin film transistor array panel and manufacturing method thereof Mar. 10, 2009
7432145 Power semiconductor device with a base region and method of manufacturing same Oct. 7, 2008
7374986 Method of fabricating field effect transistor (FET) having wire channels May. 20, 2008
7282400 Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Oct. 16, 2007
7115921 Nano-scaled gate structure with self-interconnect capabilities Oct. 3, 2006
7074657 Low-power multiple-channel fully depleted quantum well CMOSFETs Jul. 11, 2006
7049185 Semiconductor device having dummy gates and its manufacturing method May. 23, 2006
6933186 Method for BEOL resistor tolerance improvement using anodic oxidation Aug. 23, 2005
6929988 Method of making an ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge Aug. 16, 2005
6888182 Thin film transistor, method for manufacturing same, and liquid crystal display device using same May. 3, 2005
6855989 Damascene finfet gate with selective metal interdiffusion Feb. 15, 2005
6853020 Double-gate semiconductor device Feb. 8, 2005
6558996 Edge structure for relaxing electric field of semiconductor device having an embedded type diffusion structure May. 6, 2003
6551865 Silicon carbide semiconductor device and method of fabricating the same Apr. 22, 2003
6524876 Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same Feb. 25, 2003
6486011 JFET structure and manufacture method for low on-resistance and low voltage application Nov. 26, 2002
6355513 Asymmetric depletion region for normally off JFET Mar. 12, 2002
6344379 Semiconductor device with an undulating base region and method therefor Feb. 5, 2002
6251717 Viable memory cell formed using rapid thermal annealing Jun. 26, 2001
5930651 Method of forming a semiconductor device having a plurality of cavity defined gating regions Jul. 27, 1999
5923075 Definition of anti-fuse cell for programmable gate array application Jul. 13, 1999
5909615 Method for making a vertically redundant dual thin film transistor Jun. 1, 1999
5886382 Trench transistor structure comprising at least two vertical transistors Mar. 23, 1999
5814548 Process for making n-channel or p-channel permeable base transistor with a plurality layers Sep. 29, 1998
5801419 High frequency MOS device Sep. 1, 1998
5793072 Non-photosensitive, vertically redundant 2-channel .alpha.-Si:H thin film transistor Aug. 11, 1998
5739044 Method of manufacturing semiconductor device Apr. 14, 1998
5712189 Epitaxial overgrowth method Jan. 27, 1998
5705406 Method for producing a semiconductor device having semiconductor layers of SiC by the use of an ion-implantation technique Jan. 6, 1998
5686330 Method of making a self-aligned static induction transistor Nov. 11, 1997
5624860 Vertical field effect transistor and method Apr. 29, 1997

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