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Class Information
Number: 438/192
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having junction gate (e.g., jfet, sit, etc.) > Vertical channel
Description: Process for making a junction gate field effect transistor wherein the active channel is configured to provide, in whole or in part, a vertically conductive pathway between source and drain regions.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7608496 |
High speed GE channel heterostructures for field effect devices |
Oct. 27, 2009 |
| 7595261 |
Method and system for manufacturing semiconductor device having less variation in electrical characteristics |
Sep. 29, 2009 |
| 7566667 |
Methods of fabricating a semiconductor device having a barrier metal layer and devices formed thereby |
Jul. 28, 2009 |
| 7510924 |
Method for manufacturing memory cell |
Mar. 31, 2009 |
| 7485509 |
Semiconductor device provided by silicon carbide substrate and method for manufacturing the same |
Feb. 3, 2009 |
| 7432134 |
Semiconductor device and method of fabricating the same |
Oct. 7, 2008 |
| 7372087 |
Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage |
May. 13, 2008 |
| 7297580 |
Methods of fabricating transistors having buried p-type layers beneath the source region |
Nov. 20, 2007 |
| 7273771 |
Common MOSFET process for plural devices |
Sep. 25, 2007 |
| 7259048 |
Vertical replacement-gate silicon-on-insulator transistor |
Aug. 21, 2007 |
| 7256082 |
Production method for semiconductor device |
Aug. 14, 2007 |
| 7242057 |
Vertical transistor structures having vertical-surrounding-gates with self-aligned features |
Jul. 10, 2007 |
| 7135362 |
Isolation layer for CMOS image sensor and fabrication method thereof |
Nov. 14, 2006 |
| 7109516 |
Strained-semiconductor-on-insulator finFET device structures |
Sep. 19, 2006 |
| 7094637 |
Method for minimizing the vapor deposition of tungsten oxide during the selective side wall oxidation of tungsten-silicon gates |
Aug. 22, 2006 |
| 7067363 |
Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances |
Jun. 27, 2006 |
| 7033877 |
Vertical replacement-gate junction field-effect transistor |
Apr. 25, 2006 |
| 7033876 |
Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same |
Apr. 25, 2006 |
| 6995053 |
Vertical thin film transistor |
Feb. 7, 2006 |
| 6995052 |
Method and structure for double dose gate in a JFET |
Feb. 7, 2006 |
| 6933186 |
Method for BEOL resistor tolerance improvement using anodic oxidation |
Aug. 23, 2005 |
| 6929988 |
Method of making an ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge |
Aug. 16, 2005 |
| 6919241 |
Superjunction device and process for its manufacture |
Jul. 19, 2005 |
| 6855603 |
Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof |
Feb. 15, 2005 |
| 6770534 |
Ultra small size vertical MOSFET device and method for the manufacture thereof |
Aug. 3, 2004 |
| 6750095 |
Integrated circuit with vertical transistors |
Jun. 15, 2004 |
| 6744097 |
EEPROM memory cell and method of forming the same |
Jun. 1, 2004 |
| 6740910 |
Field-effect transistor, circuit configuration and method of fabricating a field-effect transistor |
May. 25, 2004 |
| 6653666 |
J-FET semiconductor configuration |
Nov. 25, 2003 |
| 6632723 |
Semiconductor device |
Oct. 14, 2003 |
| 6624032 |
Structure and process flow for fabrication of dual gate floating body integrated MOS transistors |
Sep. 23, 2003 |
| 6558996 |
Edge structure for relaxing electric field of semiconductor device having an embedded type diffusion structure |
May. 6, 2003 |
| 6551868 |
Vertical power component manufacturing method |
Apr. 22, 2003 |
| 6544824 |
Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel |
Apr. 8, 2003 |
| 6511884 |
Method to form and/or isolate vertical transistors |
Jan. 28, 2003 |
| 6482723 |
Method for forming self-aligned floating gates |
Nov. 19, 2002 |
| 6472258 |
Double gate trench transistor |
Oct. 29, 2002 |
| 6436770 |
Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation |
Aug. 20, 2002 |
| 6406934 |
Wafer level production of chip size semiconductor packages |
Jun. 18, 2002 |
| 6372564 |
Method of manufacturing V-shaped flash memory |
Apr. 16, 2002 |
| 6344379 |
Semiconductor device with an undulating base region and method therefor |
Feb. 5, 2002 |
| 6309919 |
Method for fabricating a trench-gated vertical CMOS device |
Oct. 30, 2001 |
| 6271550 |
Junction field effect transistor or JFET with a well which has graded doping directly beneath the gate electrode |
Aug. 7, 2001 |
| 6268621 |
Vertical channel field effect transistor |
Jul. 31, 2001 |
| 6239006 |
Native oxide removal with fluorinated chemistry before cobalt silicide formation |
May. 29, 2001 |
| 6225210 |
High density capping layers with improved adhesion to copper interconnects |
May. 1, 2001 |
| 6198116 |
Complementary heterostructure integrated single metal transistor fabrication method |
Mar. 6, 2001 |
| 6069384 |
Integrated circuit including vertical transistors with spacer gates having selected gate widths |
May. 30, 2000 |
| 6062869 |
Method of making a stacked thin film assembly |
May. 16, 2000 |
| 6034435 |
Metal contact structure in semiconductor device |
Mar. 7, 2000 |
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