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Class Information
Number: 438/188
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having junction gate (e.g., jfet, sit, etc.) > Complementary junction gate field effect transistors
Description: Process for making plural junction gate field effect transistors of opposite conductivity type (i.e., wherein source and drain regions of a first field effect transistor are of opposite conductivity type to source and drain regions of a second field effect transistor).
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7608496 |
High speed GE channel heterostructures for field effect devices |
Oct. 27, 2009 |
| 7605017 |
Method of manufacturing a semiconductor device and products made thereby |
Oct. 20, 2009 |
| 7572689 |
Method and structure for reducing induced mechanical stresses |
Aug. 11, 2009 |
| 7569873 |
Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys |
Aug. 4, 2009 |
| 7553718 |
Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps |
Jun. 30, 2009 |
| 7544552 |
Method for manufacturing junction semiconductor device |
Jun. 9, 2009 |
| 7504677 |
Multi-gate enhancement mode RF switch and bias arrangement |
Mar. 17, 2009 |
| 7449357 |
Method for fabricating image sensor using wafer back grinding |
Nov. 11, 2008 |
| 7238577 |
Method of manufacturing self-aligned n and p type stripes for a superjunction device |
Jul. 3, 2007 |
| 7202120 |
Semiconductor integrated circuit device and fabrication process thereof |
Apr. 10, 2007 |
| 7161544 |
Mobile terminals including a built-in radio frequency test interface |
Jan. 9, 2007 |
| 7118952 |
Method of making transistor with strained source/drain |
Oct. 10, 2006 |
| 7101744 |
Method for forming self-aligned, dual silicon nitride liner for CMOS devices |
Sep. 5, 2006 |
| 7087473 |
Method of forming conventional complementary MOS transistors and complementary heterojunction MOS transistors on common substrate |
Aug. 8, 2006 |
| 7033877 |
Vertical replacement-gate junction field-effect transistor |
Apr. 25, 2006 |
| 6861303 |
JFET structure for integrated circuit and fabrication method |
Mar. 1, 2005 |
| 6812080 |
Method of producing semiconductor device |
Nov. 2, 2004 |
| 6812077 |
Method for patterning narrow gate lines |
Nov. 2, 2004 |
| 6803265 |
Liner for semiconductor memories and manufacturing method therefor |
Oct. 12, 2004 |
| 6794232 |
Method of making MOSFET gate electrodes with tuned work function |
Sep. 21, 2004 |
| 6787437 |
Method of making a high-voltage transistor with buried conduction regions |
Sep. 7, 2004 |
| 6759289 |
Method of fabricating a high-voltage transistor |
Jul. 6, 2004 |
| 6734496 |
Semiconductor device |
May. 11, 2004 |
| 6724040 |
Semiconductor device |
Apr. 20, 2004 |
| 6613622 |
Method of forming a semiconductor device and structure therefor |
Sep. 2, 2003 |
| 6509220 |
Method of fabricating a high-voltage transistor |
Jan. 21, 2003 |
| 6489190 |
Method of fabricating a high-voltage transistor |
Dec. 3, 2002 |
| 6486011 |
JFET structure and manufacture method for low on-resistance and low voltage application |
Nov. 26, 2002 |
| 6468847 |
Method of fabricating a high-voltage transistor |
Oct. 22, 2002 |
| 6465291 |
High-voltage transistor with buried conduction layer |
Oct. 15, 2002 |
| 6309919 |
Method for fabricating a trench-gated vertical CMOS device |
Oct. 30, 2001 |
| 6251716 |
JFET structure and manufacture method for low on-resistance and low voltage application |
Jun. 26, 2001 |
| 6225153 |
Universal charge port connector for electric vehicles |
May. 1, 2001 |
| 6168983 |
Method of making a high-voltage transistor with multiple lateral conduction layers |
Jan. 2, 2001 |
| 6153453 |
JFET transistor manufacturing method |
Nov. 28, 2000 |
| 6090651 |
Depletion free polysilicon gate electrodes |
Jul. 18, 2000 |
| 5500545 |
Double switching field effect transistor and method of manufacturing it |
Mar. 19, 1996 |
| 5480829 |
Method of making a III-V complementary heterostructure device with compatible non-gold ohmic contacts |
Jan. 2, 1996 |
| 5296409 |
Method of making n-channel and p-channel junction field-effect transistors and CMOS transistors using a CMOS or bipolar/CMOS process |
Mar. 22, 1994 |
| 5290719 |
Method of making complementary heterostructure field effect transistors |
Mar. 1, 1994 |
| 5223449 |
Method of making an integrated circuit composed of group III-V compound field effect and bipolar semiconductors |
Jun. 29, 1993 |
| 5116774 |
Heterojunction method and structure |
May. 26, 1992 |
| 5010025 |
Method of making trench JFET integrated circuit elements |
Apr. 23, 1991 |
| 4912053 |
Ion implanted JFET with self-aligned source and drain |
Mar. 27, 1990 |
| 4808547 |
Method of fabrication of high voltage IC bopolar transistors operable to BV.sub.CBO |
Feb. 28, 1989 |
| 4700461 |
Process for making junction field-effect transistors |
Oct. 20, 1987 |
| 4679298 |
Method of fabrication of GaAs complementary enhancement mode junction field effect transistor |
Jul. 14, 1987 |
| 4117587 |
Negative-resistance semiconductor device |
Oct. 3, 1978 |
| 4089021 |
Semiconductor device capable of withstanding high voltage and method of manufacturing same |
May. 9, 1978 |
| 4035207 |
Process for producing an integrated circuit including a J-FET and one complementary MIS-FET |
Jul. 12, 1977 |
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