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Class Information
Number: 438/177
Name: Semiconductor device manufacturing: process > Making field effect device having pair of active regions separated by gate structure by formation or alteration of semiconductive active regions > Having schottky gate (e.g., mesfet, hemt, etc.) > Closed or loop gate
Description: Process for making a Schottky field effect transistor wherein the gate electrode is configured such that it closes upon itself to thereby totally surround one of the device active regions.










Patents under this class:

Patent Number Title Of Patent Date Issued
8361849 Method of fabricating semiconductor device Jan. 29, 2013
8329535 Multi-level-cell trapping DRAM Dec. 11, 2012
8148219 Thick oxide P-gate NMOS capacitor for use in a low-pass filter of a circuit and method of making same Apr. 3, 2012
8124961 Single electron transistor Feb. 28, 2012
8008142 Self-aligned Schottky diode Aug. 30, 2011
7989279 Method of fabricating semiconductor device Aug. 2, 2011
7910413 Structure and method of fabricating FinFET with buried channel Mar. 22, 2011
7560347 Methods for forming a wrap-around gate field effect transistor Jul. 14, 2009
7439104 Semiconductor device with increased channel length and method for fabricating the same Oct. 21, 2008
7435653 Methods for forming a wrap-around gate field effect transistor Oct. 14, 2008
7220636 Process for controlling performance characteristics of a negative differential resistance (NDR) device May. 22, 2007
6849483 Charge trapping device and method of forming the same Feb. 1, 2005
6759286 Method of fabricating a gate structure of a field effect transistor using a hard mask Jul. 6, 2004
5147812 Fabrication method for a sub-micron geometry semiconductor device Sep. 15, 1992
4729966 Process for manufacturing a Schottky FET device using metal sidewalls as gates Mar. 8, 1988











 
 
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