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Class Information
Number: 438/129
Name: Semiconductor device manufacturing: process > Making device array and selectively interconnecting > With electrical circuit layout
Description: Process including a step of designing the topological arrangement of arrayed device components or electrical conductors therebetween in combination with making the semiconductor device array.










Patents under this class:
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Patent Number Title Of Patent Date Issued
8703597 Method for fabrication of a semiconductor device and structure Apr. 22, 2014
8703546 Activation treatments in plating processes Apr. 22, 2014
8679901 Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same Mar. 25, 2014
8664044 Method of fabricating land grid array semiconductor package Mar. 4, 2014
8659139 Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate Feb. 25, 2014
8659165 Contact and VIA interconnects using metal around dielectric pillars Feb. 25, 2014
8659143 Stub minimization for wirebond assemblies without windows Feb. 25, 2014
8659142 Stub minimization for wirebond assemblies without windows Feb. 25, 2014
8659141 Stub minimization using duplicate sets of terminals for wirebond assemblies without windows Feb. 25, 2014
8659140 Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate Feb. 25, 2014
8658476 Low temperature P+ polycrystalline silicon material for non-volatile memory device Feb. 25, 2014
8658475 Stacked body-contacted field effect transistor Feb. 25, 2014
8658474 Contact and via interconnects using metal around dielectric pillars Feb. 25, 2014
8653646 Stub minimization using duplicate sets of terminals for wirebond assemblies without windows Feb. 18, 2014
8642988 Non-volatile memory device Feb. 4, 2014
8637353 Through silicon via repair Jan. 28, 2014
8623700 Inter-chip communication Jan. 7, 2014
8624300 Contact integration for three-dimensional stacking semiconductor devices Jan. 7, 2014
8614496 Method to scale down IC layout Dec. 24, 2013
8597960 Semiconductor chip stacking for redundancy and yield improvement Dec. 3, 2013
8581424 Information recording/reproducing device Nov. 12, 2013
8574968 Epitaxial methods and templates grown by the methods Nov. 5, 2013
8575703 Semiconductor device layout reducing imbalance characteristics of paired transistors Nov. 5, 2013
8557661 Methods of manufacturing a semiconductor device and a semiconductor memory device thereby Oct. 15, 2013
8561003 N-channel and P-channel finFET cell architecture with inter-block insulator Oct. 15, 2013
8561004 Ring power gating with distributed currents using non-linear contact placements Oct. 15, 2013
8546196 Non-volatile memory device and manufacturing method thereof Oct. 1, 2013
8542513 Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of read Sep. 24, 2013
8542337 Pixel structure of active matrix organic light emitting display and manufacturing thereof Sep. 24, 2013
8530939 Cross-point memory structures Sep. 10, 2013
8518756 Method for crystallizing thin film, method for manufacturing thin film semiconductor device, method for manufacturing electronic apparatus, and method for manufacturing display device Aug. 27, 2013
8513721 CMOS image sensor with non-contact structure Aug. 20, 2013
8492205 Offset geometries for area reduction in memory arrays Jul. 23, 2013
8487423 Interconnect structure of semiconductor integrated circuit and semiconductor device including the same Jul. 16, 2013
8476085 Method of fabricating dual trench isolated epitaxial diode array Jul. 2, 2013
8471387 Extendable network structure Jun. 25, 2013
8471299 Layout and pad floor plan of power transistor for good performance of SPU and STOG Jun. 25, 2013
8468692 Method of manufacturing a variable resistance memory device Jun. 25, 2013
8471325 Nonvolatile memory device and method for manufacturing the same Jun. 25, 2013
8461035 Method for fabrication of a semiconductor device and structure Jun. 11, 2013
8455939 Stacked metal fin cell Jun. 4, 2013
8450836 Semiconductor device May. 28, 2013
8451644 Non-volatile sampler May. 28, 2013
8445318 Phase change memory devices including phase change layer formed by selective growth methods and methods of manufacturing the same May. 21, 2013
8445367 Methods of manufacturing semiconductor devices May. 21, 2013
8443306 Planar compatible FDSOI design architecture May. 14, 2013
8440508 Hydrogen barrier for ferroelectric capacitors May. 14, 2013
8431446 Via formation for cross-point memory Apr. 30, 2013
8431817 Multi-junction solar cell having sidewall bi-layer electrical interconnect Apr. 30, 2013
8420453 Method of forming active region structure Apr. 16, 2013

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