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Class Information
Number: 365/69
Name: Static information storage and retrieval > Interconnection arrangements > Magnetic > Crossover
Description:










Patents under this class:
1 2 3

Patent Number Title Of Patent Date Issued
8649217 Non-volatile memory device and manufacturing method of the same Feb. 11, 2014
8542515 Connection and addressing of multi-plane crosspoint devices Sep. 24, 2013
8467219 Integrated circuit self aligned 3D memory array and manufacturing method Jun. 18, 2013
8411479 Memory circuits, systems, and methods for routing the memory circuits Apr. 2, 2013
8279403 Exposure apparatus and image forming apparatus Oct. 2, 2012
8248833 Semiconductor memory device and semiconductor device Aug. 21, 2012
8023307 Peripheral signal handling in extensible three dimensional circuits Sep. 20, 2011
7923812 Quad memory cell and method of making same Apr. 12, 2011
7835208 Multi-level dynamic memory device Nov. 16, 2010
7804700 Semiconductor memory device with reduced coupling noise Sep. 28, 2010
7761753 Memory channel with bit lane fail-over Jul. 20, 2010
7613025 Dram cell design with folded digitline architecture and angled active areas Nov. 3, 2009
7505302 Multi-level dynamic memory device Mar. 17, 2009
7414913 Bitline twisting scheme for multiport memory Aug. 19, 2008
7349232 6F.sup.2 DRAM cell design with 3F-pitch folded digitline sense amplifier Mar. 25, 2008
7310256 Semiconductor memory device Dec. 18, 2007
7277309 Interlocking memory/logic cell layout and method of manufacture Oct. 2, 2007
7257011 Semiconductor memory having twisted bit line architecture Aug. 14, 2007
7242602 Semiconductor memory devices having conductive line in twisted areas of twisted bit line pairs Jul. 10, 2007
7221577 Bus twisting scheme for distributed coupling and low power May. 22, 2007
7200059 Semiconductor memory and burn-in test method of semiconductor memory Apr. 3, 2007
7154793 Integrated memory and method for functional testing of the integrated memory Dec. 26, 2006
7139993 Method and apparatus for routing differential signals across a semiconductor chip Nov. 21, 2006
7106639 Defect management enabled PIRM and method Sep. 12, 2006
7079410 Ferroelectric memory cell array and device for operating the same Jul. 18, 2006
7075807 Magnetic memory with static magnetic offset field Jul. 11, 2006
7020012 Cross point array using distinct voltages Mar. 28, 2006
6999336 Ferroelectric memory Feb. 14, 2006
6909663 Multiport memory with twisted bitlines Jun. 21, 2005
6894231 Bus twisting scheme for distributed coupling and low power May. 17, 2005
6873537 Ferroelectric memory cell array and device for operating the same Mar. 29, 2005
6870754 Ferroelectric memory Mar. 22, 2005
6862234 Method and test circuit for testing a dynamic memory circuit Mar. 1, 2005
6862204 Semiconductor integrated circuit having connecting wires for interconnecting bit lines Mar. 1, 2005
6845028 Semiconductor memory device using open data line arrangement Jan. 18, 2005
6839266 Memory module with offset data lines and bit line swizzle configuration Jan. 4, 2005
6831854 Cross point memory array using distinct voltages Dec. 14, 2004
6826075 Random access semiconductor memory with reduced signal overcoupling Nov. 30, 2004
6704220 Layout for thermally selected cross-point MRAM cell Mar. 9, 2004
6693816 Reversed memory module socket, motherboard and test system including same, and method of modifying motherboard Feb. 17, 2004
6693817 Reversed memory module socket, motherboard and test system including same, and method of modifying motherboard Feb. 17, 2004
6671198 Semiconductor device Dec. 30, 2003
6665204 Semiconductor memory device for decreasing a coupling capacitance Dec. 16, 2003
6657880 SRAM bit line architecture Dec. 2, 2003
6584029 One-time programmable memory using fuse/anti-fuse and vertically oriented fuse unit memory cells Jun. 24, 2003
6544850 Dynamic random access memory Apr. 8, 2003
6538912 Semiconductor device Mar. 25, 2003
6519174 Early write DRAM architecture with vertically folded bitlines Feb. 11, 2003
6498758 Twisted bitlines to reduce coupling effects (dual port memories) Dec. 24, 2002
6480408 Twisted global column decoder Nov. 12, 2002

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