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Class Information
Number: 365/233
Name: Static information storage and retrieval > Addressing > Sync/clocking
Description: Subject matter where synchronizing and clocking circuits are used to select a memory location.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7289385 |
Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method |
Oct. 30, 2007 |
| 7289379 |
Memory devices and methods of operation thereof using interdependent sense amplifier control |
Oct. 30, 2007 |
| 7289377 |
Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device |
Oct. 30, 2007 |
| 7287119 |
Integrated circuit memory device with delayed write command processing |
Oct. 23, 2007 |
| 7286441 |
Integrated memory controller |
Oct. 23, 2007 |
| 7286440 |
Pseudo SRAM with common pad for address pin and data pin |
Oct. 23, 2007 |
| 7286432 |
Temperature update masking to ensure correct measurement of temperature when references become unstable |
Oct. 23, 2007 |
| 7286423 |
Bit line precharge in embedded memory |
Oct. 23, 2007 |
| 7286415 |
Semiconductor memory devices having a dual port mode and methods of operating the same |
Oct. 23, 2007 |
| 7286397 |
Clock synchronized nonvolatile memory device |
Oct. 23, 2007 |
| 7283421 |
Semiconductor memory device |
Oct. 16, 2007 |
| 7283404 |
Content addressable memory including a dual mode cycle boundary latch |
Oct. 16, 2007 |
| 7280431 |
Method of generating an internal clock for a semiconductor memory device and semiconductor memory device using the same |
Oct. 9, 2007 |
| 7280430 |
Semiconductor memory device |
Oct. 9, 2007 |
| 7280429 |
Data latch circuit of semiconductor device and method for latching data signal |
Oct. 9, 2007 |
| 7280419 |
Latency counter having frequency detector and latency counting method thereof |
Oct. 9, 2007 |
| 7280406 |
Semiconductor memory device |
Oct. 9, 2007 |
| 7277357 |
Method and apparatus for reducing oscillation in synchronous circuits |
Oct. 2, 2007 |
| 7277354 |
Apparatus and method for updating data in a dual port memory |
Oct. 2, 2007 |
| 7277340 |
Smart memory read out for power saving |
Oct. 2, 2007 |
| 7277334 |
Method and apparatus for synchronization of row and column access operations |
Oct. 2, 2007 |
| 7277332 |
Method and circuit for elastic storing capable of adapting to high-speed data communications |
Oct. 2, 2007 |
| 7274620 |
Semiconductor memory device |
Sep. 25, 2007 |
| 7274606 |
Low power chip select (CS) latency option |
Sep. 25, 2007 |
| 7274605 |
Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM |
Sep. 25, 2007 |
| 7272071 |
Systems and methods that employ inductive current steering for digital logic circuits |
Sep. 18, 2007 |
| 7272069 |
Multiple-clock controlled logic signal generating circuit |
Sep. 18, 2007 |
| 7272056 |
Data output controller in semiconductor memory device and control method thereof |
Sep. 18, 2007 |
| 7272054 |
Time domain bridging circuitry for use in determining output enable timing |
Sep. 18, 2007 |
| 7269094 |
Memory system and method for strobing data, command and address signals |
Sep. 11, 2007 |
| 7269093 |
Generating a sampling clock signal in a communication block of a memory device |
Sep. 11, 2007 |
| 7266039 |
Circuitry and method for adjusting signal length |
Sep. 4, 2007 |
| 7266038 |
Method for activating and deactivating electronic circuit units and circuit arrangement for carrying out the method |
Sep. 4, 2007 |
| 7266032 |
Memory device having low Vpp current consumption |
Sep. 4, 2007 |
| 7266022 |
Memory interface control circuit |
Sep. 4, 2007 |
| 7263026 |
Semiconductor memory device and method for controlling the same |
Aug. 28, 2007 |
| 7263025 |
Semiconductor memory device for stably controlling power mode at high frequency and method of controlling power mode thereof |
Aug. 28, 2007 |
| 7263024 |
Clock reset address decoder for block memory |
Aug. 28, 2007 |
| 7263015 |
Address decoding |
Aug. 28, 2007 |
| 7263013 |
Synchronous memory device capable of controlling write recovery time |
Aug. 28, 2007 |
| 7263009 |
Semiconductor memory device with delay section |
Aug. 28, 2007 |
| 7262986 |
Memory system and semiconductor integrated circuit |
Aug. 28, 2007 |
| 7260493 |
Testing a device under test by sampling its clock and data signal |
Aug. 21, 2007 |
| 7260020 |
Synchronous global controller for enhanced pipelining |
Aug. 21, 2007 |
| 7260013 |
Power supply device in semiconductor memory |
Aug. 21, 2007 |
| 7257725 |
Memory system |
Aug. 14, 2007 |
| 7254090 |
Semiconductor memory device |
Aug. 7, 2007 |
| 7254076 |
Semiconductor memory device for improving response margin of redundancy flag signal and redundancy driving method for the same |
Aug. 7, 2007 |
| 7251715 |
Double data rate scheme for data output |
Jul. 31, 2007 |
| 7251711 |
Apparatus and methods having a command sequence |
Jul. 31, 2007 |
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