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Class Information
Number: 365/233.13
Name: Static information storage and retrieval >
Description:










Sub-classes under this class:

Class Number Class Name Patents
365/1 Magnetic bubbles 135
365/106 Radiant energy 185
365/120 Information masking 98
365/129 Systems using particular element 131
365/185.01 Floating gate 820
365/189.01 Read/write circuit 1,848
365/226 Powering 3,189
365/230.01 Addressing 1,140
365/244 Miscellaneous 49
365/45 Analog storage systems 259
365/49 Associative memories 1,168
365/51 Format or disposition of elements 1,892
365/52 Hardware for storage elements 494
365/63 Interconnection arrangements 3,180
365/73 Recirculation stores 82
365/78 Plural shift register memory devices 187
365/80 Magnetic shift registers 68
365/94 Read only systems (i.e.. semipermanent) 492


Patents under this class:

Patent Number Title Of Patent Date Issued
8711643 Memory interface circuit, memory interface method, and electronic device Apr. 29, 2014
8711651 System and method for managing self-refresh in a multi-rank memory Apr. 29, 2014
8705310 Access methods and circuits for memory devices having multiple banks Apr. 22, 2014
8705313 DDR PSRAM and data writing and reading methods thereof Apr. 22, 2014
8687457 Semiconductor memory device and operating method thereof Apr. 1, 2014
8687459 Synchronous command-based write recovery time auto-precharge control Apr. 1, 2014
8681571 Training a memory controller and a memory device using multiple read and write operations Mar. 25, 2014
8665653 Memory system and control method therefor Mar. 4, 2014
8661285 Dynamically calibrated DDR memory controller Feb. 25, 2014
8654556 Registered DIMM memory system Feb. 18, 2014
8654603 Test operation for a low-power double-data-rate (LPDDR) nonvolatile memory device Feb. 18, 2014
8649210 DDR PSRAM and data writing and reading methods thereof Feb. 11, 2014
8644106 Shift circuit of a semiconductor device Feb. 4, 2014
8638629 Refresh control circuit, memory apparatus and refresh control method using the same Jan. 28, 2014
8634269 Data output circuit of semiconductor memory apparatus Jan. 21, 2014
8630111 Memory devices and methods for high random transaction rate Jan. 14, 2014
8630131 Data strobe enable circuitry Jan. 14, 2014
8625385 Data capture system and method, and memory controllers and devices Jan. 7, 2014
8619486 Semiconductor memory device incorporating an interface chip for selectively refreshing memory cells in core chips Dec. 31, 2013
8611170 Mechanisms for utilizing efficiency metrics to control embedded dynamic random access memory power states on a semiconductor integrated circuit package Dec. 17, 2013
8611178 Device and method to perform memory operations at a clock domain crossing Dec. 17, 2013
8605539 Hardware-based data eye training for high speed links Dec. 10, 2013
8599634 Circuit and method for refreshing a memory module Dec. 3, 2013
8601231 Semiconductor memory asynchronous pipeline Dec. 3, 2013
8594114 Shielding of datalines with physical placement based on time staggered access Nov. 26, 2013
8593902 Controller and access method for DDR PSRAM and operating method thereof Nov. 26, 2013
8582392 Non-volatile memory devices for outputting data using double data rate (DDR) operations and methods of operating the same Nov. 12, 2013
8570790 Memory devices and methods for high random transaction rate Oct. 29, 2013
8570816 Digital memory system that dynamically adjusts reference voltage as a function of traffic intensity Oct. 29, 2013
8565033 Methods for calibrating memory interface circuitry Oct. 22, 2013
8553489 Semiconductor device having point-shift type FIFO circuit Oct. 8, 2013
8547761 Memory module and memory system comprising memory module Oct. 1, 2013
8531897 Delay control circuit and semiconductor memory device including the same Sep. 10, 2013
8531909 Delay-locked loop having loop bandwidth dependency on operating frequency Sep. 10, 2013
8526267 Electronic device Sep. 3, 2013
8526249 Methods and systems for detecting and correcting timing signal drift in memory systems Sep. 3, 2013
8514635 Memory system and control method therefor Aug. 20, 2013
8488408 Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocks Jul. 16, 2013
8483005 Internal signal generator for use in semiconductor memory device Jul. 9, 2013
8477543 Data input circuit with a valid strobe signal generation circuit Jul. 2, 2013
8456928 Dynamic adjustment of reference voltage in a computer memory system Jun. 4, 2013
8448010 Increasing memory bandwidth in processor-based systems May. 21, 2013
8422263 Load reduced memory module and memory system including the same Apr. 16, 2013
8411517 Delay locked loop circuit including delay line with reduced sensitivity to variation in PVT Apr. 2, 2013
8406071 Strobe apparatus, systems, and methods Mar. 26, 2013
8406080 Data output control circuit of a double data rate (DDR) synchronous semiconductor memory device responsive to a delay locked loop (DLL) clock and method thereof Mar. 26, 2013
8400869 Semiconductor memory module Mar. 19, 2013
8400805 Semiconductor device Mar. 19, 2013
8395946 Data access apparatus and associated method for accessing data using internally generated clocks Mar. 12, 2013
8391089 Method and circuit of calibrating data strobe signal in memory controller Mar. 5, 2013











 
 
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