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Class Information
Number: 365/230.09
Name: Static information storage and retrieval > Addressing > Combined random and sequential addressing
Description: Subject matter including switching to permit the access to the storage elements either selectively or successively.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7599214 |
Semiconductor memory device |
Oct. 6, 2009 |
| 7573733 |
Self-identifying stacked die semiconductor components |
Aug. 11, 2009 |
| 7558148 |
Memory controller |
Jul. 7, 2009 |
| 7558142 |
Method and system for controlling refresh to avoid memory cell data losses |
Jul. 7, 2009 |
| 7554874 |
Method and apparatus for mapping memory |
Jun. 30, 2009 |
| 7551502 |
Semiconductor device |
Jun. 23, 2009 |
| 7539077 |
Flash memory device having a data buffer and programming method of the same |
May. 26, 2009 |
| 7499372 |
Semiconductor memory device |
Mar. 3, 2009 |
| 7495993 |
Onboard data storage and method |
Feb. 24, 2009 |
| 7489583 |
Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays |
Feb. 10, 2009 |
| 7471545 |
Semiconductor memory device |
Dec. 30, 2008 |
| 7457185 |
Semiconductor memory device with advanced refresh control |
Nov. 25, 2008 |
| 7436689 |
Non-volatile semiconductor memory |
Oct. 14, 2008 |
| 7433258 |
Posted precharge and multiple open-page RAM architecture |
Oct. 7, 2008 |
| 7352648 |
Semiconductor memory |
Apr. 1, 2008 |
| 7319634 |
Address converter semiconductor device and semiconductor memory device having the same |
Jan. 15, 2008 |
| 7272066 |
Method and system for controlling refresh to avoid memory cell data losses |
Sep. 18, 2007 |
| 7266020 |
Method and apparatus for address and data line usage in a multiple context programmable logic device |
Sep. 4, 2007 |
| 7266038 |
Method for activating and deactivating electronic circuit units and circuit arrangement for carrying out the method |
Sep. 4, 2007 |
| 7254690 |
Pipelined semiconductor memories and systems |
Aug. 7, 2007 |
| 7239573 |
Method of storing data in blocks per operation |
Jul. 3, 2007 |
| 7212448 |
Method and apparatus for multiple context and high reliability operation of programmable logic devices |
May. 1, 2007 |
| 7193928 |
Signal output device and method for the same |
Mar. 20, 2007 |
| 7167404 |
Method and device for testing configuration memory cells in programmable logic devices (PLDS) |
Jan. 23, 2007 |
| 7142476 |
Refresh counter circuit and control method for refresh operation |
Nov. 28, 2006 |
| 7124256 |
Memory device for burst or pipelined operation with mode selection circuitry |
Oct. 17, 2006 |
| 7120078 |
Synchronous semiconductor memory |
Oct. 10, 2006 |
| 7116602 |
Method and system for controlling refresh to avoid memory cell data losses |
Oct. 3, 2006 |
| 7099229 |
Nonvolatile memory device having circuit for stably supplying desired current during data writing |
Aug. 29, 2006 |
| 7099179 |
Conductive memory array having page mode and burst mode write capability |
Aug. 29, 2006 |
| 7072923 |
Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses |
Jul. 4, 2006 |
| 7057946 |
Semiconductor integrated circuit having latching means capable of scanning |
Jun. 6, 2006 |
| 7054218 |
Serial memory address decoding scheme |
May. 30, 2006 |
| 7042795 |
Flash memory device with burst read mode of operation |
May. 9, 2006 |
| 7016254 |
Synchronous flash memory with virtual segment architecture |
Mar. 21, 2006 |
| 6999376 |
Burst read addressing in a non-volatile memory device |
Feb. 14, 2006 |
| 6973006 |
Predecode column architecture and method |
Dec. 6, 2005 |
| 6947302 |
Multi-match detection circuit for use with content-addressable memories |
Sep. 20, 2005 |
| 6944714 |
Method and apparatus for saving microprocessor power when sequentially accessing the microprocessor's instruction cache |
Sep. 13, 2005 |
| 6925543 |
Burst transfer memory |
Aug. 2, 2005 |
| 6915407 |
Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller |
Jul. 5, 2005 |
| 6912615 |
Control means for burst access control |
Jun. 28, 2005 |
| 6910096 |
SDRAM with command decoder coupled to address registers |
Jun. 21, 2005 |
| 6898662 |
Memory system sectors |
May. 24, 2005 |
| 6895465 |
SDRAM with command decoder, address registers, multiplexer, and sequencer |
May. 17, 2005 |
| 6894935 |
Memory data interface |
May. 17, 2005 |
| 6874058 |
Content addressed memories |
Mar. 29, 2005 |
| 6854040 |
Non-volatile memory device with burst mode reading and corresponding reading method |
Feb. 8, 2005 |
| 6847570 |
Semiconductor memory having burst transfer function and internal refresh function |
Jan. 25, 2005 |
| 6845057 |
DDR synchronous flash memory with virtual segment architecture |
Jan. 18, 2005 |
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