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Class Information
Number: 365/230.02
Name: Static information storage and retrieval > Addressing > Multiplexing
Description: Subject matter which includes the transmission of plural signals over a single signal path.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7613023 |
Memory arrangement, particularly for the non-volatile storage of uncompressed video and/or audio data |
Nov. 3, 2009 |
| 7609538 |
Logic process DRAM |
Oct. 27, 2009 |
| 7609580 |
Redundancy program circuit and methods thereof |
Oct. 27, 2009 |
| 7606081 |
Device programmable to operate as a multiplexer, demultiplexer, or memory device |
Oct. 20, 2009 |
| 7606090 |
Redundancy program circuit and methods thereof |
Oct. 20, 2009 |
| 7602655 |
Embedded system |
Oct. 13, 2009 |
| 7599237 |
Memory device and method for precharging a memory device |
Oct. 6, 2009 |
| 7596049 |
Semiconductor memory device with a plurality of bank groups each having a plurality of banks sharing a global line group |
Sep. 29, 2009 |
| 7596011 |
Logic process DRAM |
Sep. 29, 2009 |
| 7592851 |
High performance pseudo dynamic pulse controllable multiplexer |
Sep. 22, 2009 |
| 7593271 |
Memory device including multiplexed inputs |
Sep. 22, 2009 |
| 7590009 |
Semiconductor memory apparatus and data masking method of the same |
Sep. 15, 2009 |
| 7590024 |
Nonvolatile semiconductor memory device |
Sep. 15, 2009 |
| 7580294 |
Semiconductor memory device comprising two rows of pads |
Aug. 25, 2009 |
| 7570542 |
Circuit and method for generating data output control signal for semiconductor integrated circuit |
Aug. 4, 2009 |
| 7570077 |
Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements |
Aug. 4, 2009 |
| 7564733 |
Memory device and method having programmable address configurations |
Jul. 21, 2009 |
| 7561481 |
Memory controllers and pad sequence control methods thereof |
Jul. 14, 2009 |
| 7558127 |
Data output circuit and method in DDR synchronous semiconductor device |
Jul. 7, 2009 |
| 7551512 |
Dual-port memory |
Jun. 23, 2009 |
| 7548483 |
Memory device and method having multiple address, data and command buses |
Jun. 16, 2009 |
| 7549033 |
Dual edge command |
Jun. 16, 2009 |
| 7545691 |
Measuring circuit for qualifying a memory located on a semiconductor device |
Jun. 9, 2009 |
| 7542324 |
FPGA equivalent input and output grid muxing on structural ASIC memory |
Jun. 2, 2009 |
| 7539811 |
Scaleable memory systems using third dimension memory |
May. 26, 2009 |
| 7535772 |
Configurable data path architecture and clocking scheme |
May. 19, 2009 |
| 7532512 |
Non-volatile memory device and method of handling a datum read from a memory cell |
May. 12, 2009 |
| 7529139 |
N-port memory circuits allowing M memory addresses to be accessed concurrently and signal processing methods thereof |
May. 5, 2009 |
| 7529149 |
Memory system and method with serial and parallel modes |
May. 5, 2009 |
| 7525842 |
Increased NAND flash memory read throughput |
Apr. 28, 2009 |
| 7512018 |
Column address enable signal generation circuit for semiconductor memory device |
Mar. 31, 2009 |
| 7505353 |
Multi-port semiconductor memory device having variable access paths and method |
Mar. 17, 2009 |
| 7502276 |
Method and apparatus for multi-word write in domino read SRAMs |
Mar. 10, 2009 |
| 7499364 |
Multi-port semiconductor memory device and signal input/output method therefor |
Mar. 3, 2009 |
| 7495979 |
Method and system for in-situ parametric SRAM diagnosis |
Feb. 24, 2009 |
| 7495974 |
Delay selecting circuit for semiconductor memory device |
Feb. 24, 2009 |
| 7493467 |
Address scrambling to simplify memory controller's address output multiplexer |
Feb. 17, 2009 |
| 7489583 |
Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays |
Feb. 10, 2009 |
| 7489587 |
Semiconductor memory device capable of controlling clock cycle time for reduced power consumption |
Feb. 10, 2009 |
| 7480201 |
Daisy chainable memory chip |
Jan. 20, 2009 |
| 7477568 |
Using common mode differential data signals of DDR2 SDRAM for control signal transmission |
Jan. 13, 2009 |
| 7477551 |
Systems and methods for reading data from a memory array |
Jan. 13, 2009 |
| 7471573 |
Integrated circuit device and electronic instrument |
Dec. 30, 2008 |
| 7463544 |
Device programmable to operate as a multiplexer, demultiplexer, or memory device |
Dec. 9, 2008 |
| 7450461 |
Semiconductor memory device and transmission/reception system provided with the same |
Nov. 11, 2008 |
| 7443744 |
Method for reducing wiring and required number of redundant elements |
Oct. 28, 2008 |
| 7440335 |
Contention-free hierarchical bit line in embedded memory and method thereof |
Oct. 21, 2008 |
| 7436688 |
Priority encoder circuit and method |
Oct. 14, 2008 |
| 7436726 |
Circuit for and method of reading data in an asynchronous FIFO including a backup address circuit for re-reading data |
Oct. 14, 2008 |
| 7430137 |
Non-volatile memory cells in a field programmable gate array |
Sep. 30, 2008 |
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