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Class Information
Number: 365/221
Name: Static information storage and retrieval > Read/write circuit > Serial read/write
Description: Subject matter wherein information is written into a memory in serial form and read out in serial form.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7420869 |
Memory device, use thereof and method for synchronizing a data word |
Sep. 2, 2008 |
| 7397684 |
Semiconductor memory array with serial control/address bus |
Jul. 8, 2008 |
| 7397717 |
Serial peripheral interface memory device with an accelerated parallel mode |
Jul. 8, 2008 |
| 7397727 |
Write burst stop function in low power DDR sDRAM |
Jul. 8, 2008 |
| 7394710 |
Auto-recovery fault tolerant memory synchronization |
Jul. 1, 2008 |
| 7394715 |
Memory system comprising memories with different capacities and storing and reading method thereof |
Jul. 1, 2008 |
| 7382637 |
Block-writable content addressable memory device |
Jun. 3, 2008 |
| 7379383 |
Methods of DDR receiver read re-synchronization |
May. 27, 2008 |
| 7376021 |
Data output circuit and method in DDR synchronous semiconductor device |
May. 20, 2008 |
| 7376041 |
Semiconductor memory device and data read and write method of the same |
May. 20, 2008 |
| 7372755 |
On-chip storage memory for storing variable data bits |
May. 13, 2008 |
| 7366042 |
Defective column(s) in a memory device/card is/are skipped while serial data programming is performed |
Apr. 29, 2008 |
| 7355878 |
Programmable logic devices optionally convertible to one time programmable devices |
Apr. 8, 2008 |
| 7355917 |
Two-dimensional data memory |
Apr. 8, 2008 |
| 7352648 |
Semiconductor memory |
Apr. 1, 2008 |
| 7353356 |
High speed, low current consumption FIFO circuit |
Apr. 1, 2008 |
| 7333381 |
Circuitry and methods for efficient FIFO memory |
Feb. 19, 2008 |
| 7321520 |
Configurable length first-in first-out memory |
Jan. 22, 2008 |
| 7315479 |
Redundant memory incorporating serially-connected relief information storage |
Jan. 1, 2008 |
| 7313639 |
Memory system and device with serialized data transfer |
Dec. 25, 2007 |
| 7310276 |
Memory device and method having data path with multiple prefetch I/O configurations |
Dec. 18, 2007 |
| 7304909 |
Control unit for deactivating and activating the control signals |
Dec. 4, 2007 |
| 7280417 |
System and method for capturing data signals using a data strobe signal |
Oct. 9, 2007 |
| 7263019 |
Serial presence detect functionality on memory component |
Aug. 28, 2007 |
| 7260008 |
Asynchronous first-in-first-out cell |
Aug. 21, 2007 |
| 7254079 |
Electrical fuse circuit |
Aug. 7, 2007 |
| 7245552 |
Parallel data path architecture |
Jul. 17, 2007 |
| 7237048 |
Memory system and device with serialized data transfer |
Jun. 26, 2007 |
| 7227790 |
NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device |
Jun. 5, 2007 |
| 7216187 |
Memory system including a circuit to convert between parallel and serial bits |
May. 8, 2007 |
| 7209397 |
Memory device with clock multiplier circuit |
Apr. 24, 2007 |
| 7205792 |
Methods and circuitry for implementing first-in first-out structure |
Apr. 17, 2007 |
| 7196962 |
Packet addressing programmable dual port memory devices and related methods |
Mar. 27, 2007 |
| 7184322 |
Semiconductor memory device and control method thereof |
Feb. 27, 2007 |
| 7177135 |
On-chip bypass capacitor and method of manufacturing the same |
Feb. 13, 2007 |
| 7173863 |
Flash controller cache architecture |
Feb. 6, 2007 |
| 7174432 |
Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture |
Feb. 6, 2007 |
| 7167410 |
Memory system and memory device having a serial interface |
Jan. 23, 2007 |
| 7167404 |
Method and device for testing configuration memory cells in programmable logic devices (PLDS) |
Jan. 23, 2007 |
| 7167024 |
Methods and circuitry for implementing first-in first-out structure |
Jan. 23, 2007 |
| 7158440 |
FIFO memory devices having write and read control circuits that support x4N, x2N and xN data widths during DDR and SDR modes of operation |
Jan. 2, 2007 |
| 7158442 |
Flexible latency in flash memory |
Jan. 2, 2007 |
| 7154983 |
Method of operating a first-in first-out (FIFO) circuit |
Dec. 26, 2006 |
| 7154984 |
FIFO-register and digital signal processor comprising a FIFO-register |
Dec. 26, 2006 |
| 7151707 |
Memory device and method having data path with multiple prefetch I/O configurations |
Dec. 19, 2006 |
| 7151705 |
Non-volatile memory device architecture, for instance a flash kind, having a serial communication interface |
Dec. 19, 2006 |
| 7149139 |
Circuitry and methods for efficient FIFO memory |
Dec. 12, 2006 |
| 7145831 |
Data synchronization arrangement |
Dec. 5, 2006 |
| 7142474 |
Magnetic memory device and recording control method for magnetic memory device |
Nov. 28, 2006 |
| 7139207 |
Memory interface methods and apparatus |
Nov. 21, 2006 |
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