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Class Information
Number: 365/219
Name: Static information storage and retrieval > Read/write circuit > Sipo/piso
Description: Subject matter in which the read/write circuit for memory provides Serial Input with Parallel Output or Parallel Input with Serial Output.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7616518 |
Multi-port memory device with serial input/output interface |
Nov. 10, 2009 |
| 7596046 |
Data conversion circuit, and semiconductor memory apparatus using the same |
Sep. 29, 2009 |
| 7577039 |
Memory interface to bridge memory buses |
Aug. 18, 2009 |
| 7567476 |
Semiconductor memory device and testing method thereof |
Jul. 28, 2009 |
| 7522459 |
Data input circuit of semiconductor memory device |
Apr. 21, 2009 |
| 7522458 |
Memory and method of controlling access to memory |
Apr. 21, 2009 |
| 7522440 |
Data input and data output control device and method |
Apr. 21, 2009 |
| 7519751 |
Method of generating an enable signal of a standard memory core and relative memory device |
Apr. 14, 2009 |
| 7515471 |
Memory with output control |
Apr. 7, 2009 |
| 7436725 |
Data generator having stable duration from trigger arrival to data output start |
Oct. 14, 2008 |
| 7426144 |
Semiconductor storage device |
Sep. 16, 2008 |
| 7420865 |
Pipe latch circuit for increasing data output speed, a semiconductor memory device with the pipe latch circuit and data output operation method of the same |
Sep. 2, 2008 |
| 7397717 |
Serial peripheral interface memory device with an accelerated parallel mode |
Jul. 8, 2008 |
| 7385844 |
Semiconductor device and method of controlling the same |
Jun. 10, 2008 |
| 7376041 |
Semiconductor memory device and data read and write method of the same |
May. 20, 2008 |
| 7366042 |
Defective column(s) in a memory device/card is/are skipped while serial data programming is performed |
Apr. 29, 2008 |
| 7349289 |
Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM |
Mar. 25, 2008 |
| 7336554 |
Semiconductor memory device having a reduced number of pins |
Feb. 26, 2008 |
| 7263018 |
Compensating a long read time of a memory device in data comparison and write operations |
Aug. 28, 2007 |
| 7230858 |
Dual frequency first-in-first-out structure |
Jun. 12, 2007 |
| 7227808 |
Semiconductor memory device which compensates for delay time variations of multi-bit data |
Jun. 5, 2007 |
| 7206242 |
Semiconductor memory |
Apr. 17, 2007 |
| 7196962 |
Packet addressing programmable dual port memory devices and related methods |
Mar. 27, 2007 |
| 7184360 |
High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips |
Feb. 27, 2007 |
| 7184323 |
4N pre-fetch memory data transfer system |
Feb. 27, 2007 |
| 7167404 |
Method and device for testing configuration memory cells in programmable logic devices (PLDS) |
Jan. 23, 2007 |
| 7151707 |
Memory device and method having data path with multiple prefetch I/O configurations |
Dec. 19, 2006 |
| 7075846 |
Apparatus for interleave and method thereof |
Jul. 11, 2006 |
| 7057959 |
Semiconductor memory having mode register access in burst mode |
Jun. 6, 2006 |
| 7054202 |
High burst rate write data paths for integrated circuit memory devices and methods of operating same |
May. 30, 2006 |
| 7031215 |
Memory device and method having data path with multiple prefetch I/O configurations |
Apr. 18, 2006 |
| 7016237 |
Data input circuit and method for synchronous semiconductor memory device |
Mar. 21, 2006 |
| 6990043 |
Semiconductor integrated circuit device having a common DRAM block accessed by a plurality of logic circuits |
Jan. 24, 2006 |
| 6954395 |
String programmable nonvolatile memory with NOR architecture |
Oct. 11, 2005 |
| 6952756 |
Method and apparatus for speculative loading of a memory |
Oct. 4, 2005 |
| 6944073 |
Semiconductor integrated circuit device |
Sep. 13, 2005 |
| 6930929 |
Simultaneous read-write memory cell at the bit level for a graphics display |
Aug. 16, 2005 |
| 6915175 |
Method and device for programming nonvolatile semiconductor memory |
Jul. 5, 2005 |
| 6898139 |
Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation |
May. 24, 2005 |
| 6882579 |
Memory device and method having data path with multiple prefetch I/O configurations |
Apr. 19, 2005 |
| 6879535 |
Approach for zero dummy byte flash memory read operation |
Apr. 12, 2005 |
| 6842391 |
Semiconductor memory of a dynamic random access memory (DRAM) type having a static random access memory (SRAM) interface |
Jan. 11, 2005 |
| 6819616 |
Serial to parallel data input methods and related input buffers |
Nov. 16, 2004 |
| 6735138 |
Integrated memory using prefetch architecture and method for operating an integrated memory |
May. 11, 2004 |
| 6728162 |
Data input circuit and method for synchronous semiconductor memory device |
Apr. 27, 2004 |
| 6707756 |
System and method for translation of SDRAM and DDR signals |
Mar. 16, 2004 |
| 6681314 |
FIFO memory device suitable for data transfer apparatuses with different data bus widths and method for controlling the same |
Jan. 20, 2004 |
| 6646939 |
Low power type Rambus DRAM |
Nov. 11, 2003 |
| 6606272 |
Method and circuit for processing output data in pipelined circuits |
Aug. 12, 2003 |
| 6600691 |
High frequency range four bit prefetch output data path |
Jul. 29, 2003 |
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