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Class Information
Number: 365/206
Name: Static information storage and retrieval > Read/write circuit > Noise suppression
Description: Subject matter having circuits for the cancellation or reduction of noise or spurious signals.










Sub-classes under this class:

Class Number Class Name Patents
365/207 Differential sensing 2,303
365/214 Particular wiring 151
365/211 Temperature compensation 441


Patents under this class:
1 2 3 4 5 6 7 8 9 10 11

Patent Number Title Of Patent Date Issued
6822891 Ferroelectric memory device Nov. 23, 2004
6791864 Column voltage control for write Sep. 14, 2004
6785189 Method and apparatus for improving noise immunity in a DDR SDRAM system Aug. 31, 2004
6781873 Non-volatile memory device capable of generating accurate reference current for determination Aug. 24, 2004
6760269 Semiconductor memory device capable of generating internal data read timing precisely Jul. 6, 2004
6760248 Voltage regulator with distributed output transistor Jul. 6, 2004
6754746 Memory array with read/write methods Jun. 22, 2004
6754129 Memory module with integrated bus termination Jun. 22, 2004
6735136 Semiconductor memory device capable of preventing coupling noise between adjacent bit lines in different columns May. 11, 2004
6735146 System and method for pulling electrically isolated memory cells in a memory array to a non-floating state May. 11, 2004
6735134 Semiconductor memory device and method for driving a sense amplifier May. 11, 2004
6724667 Data memory with redundant memory cells used for buffering a supply voltage Apr. 20, 2004
6721222 Noise suppression for open bit line DRAM architectures Apr. 13, 2004
6717874 Systems and methods for reducing the effect of noise while reading data in series from memory Apr. 6, 2004
6714479 Semiconductor memory and control method Mar. 30, 2004
6714470 High-speed read-write circuitry for semi-conductor memory devices Mar. 30, 2004
6687175 Semiconductor device Feb. 3, 2004
6683818 Asynchronous random access memory with power optimizing clock Jan. 27, 2004
6678197 Systems and methods for reducing the effect of noise while reading data from memory Jan. 13, 2004
6667923 RAM data array configured to provide data-independent, write cycle coherent current drain Dec. 23, 2003
6654277 SRAM with improved noise sensitivity Nov. 25, 2003
6625070 Semiconductor memory device Sep. 23, 2003
6597619 Actively driven VREF for input buffer noise immunity Jul. 22, 2003
6594173 Method for digit line architecture for dynamic memory Jul. 15, 2003
6574127 System and method for reducing noise of congested datalines in an eDRAM Jun. 3, 2003
6570781 Logic process DRAM May. 27, 2003
6567298 Semiconductor memory device and control method thereof May. 20, 2003
6567336 Semiconductor memory for logic-hybrid memory May. 20, 2003
6538946 Semiconductor integrated circuit device Mar. 25, 2003
6535451 Semiconductor memory Mar. 18, 2003
6525977 Circuit configuration Feb. 25, 2003
6525976 Systems and methods for reducing noise in mixed-mode integrated circuits Feb. 25, 2003
6525979 Semiconductor memory device and method for reading information of therefrom Feb. 25, 2003
6522594 Memory array incorporating noise detection line Feb. 18, 2003
6512714 Semiconductor memory device equipped with dummy cells Jan. 28, 2003
6473468 Data transmission device Oct. 29, 2002
6469946 Semiconductor memory and its test method Oct. 22, 2002
6466499 DRAM sense amplifier having pre-charged transistor body nodes Oct. 15, 2002
6466498 Discontinuity-based memory cell sensing Oct. 15, 2002
6462999 Semiconductor memory device having internal data read circuit excellent in noise immunity Oct. 8, 2002
6459639 Semiconductor memory device Oct. 1, 2002
6456548 Sense amplifier circuit and semiconductor storage device Sep. 24, 2002
6456549 Sense amplifier circuit and semiconductor storage device Sep. 24, 2002
6449204 DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING DATA STORAGE FROM A ONE BIT/ONE CELL SCHEME IN A NORMAL MODE TO A ONE BIT/TWO CELL SCHEME IN A TWIN-CELL MODE FOR LENGTHENING A REFRE Sep. 10, 2002
6445632 Semiconductor memory device for fast access Sep. 3, 2002
6434072 Row decoded biasing of sense amplifier for improved one's margin Aug. 13, 2002
6418044 Method and circuit for determining sense amplifier sensitivity Jul. 9, 2002
6392303 Digit line architecture for dynamic memory May. 21, 2002
6385107 Architecture for handling internal voltages in a non-volatile memory, particularly in a single-voltage supply type of dual-work flash memory May. 7, 2002
6366502 Circuitry for reading from and writing to memory cells Apr. 2, 2002

1 2 3 4 5 6 7 8 9 10 11










 
 
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