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Class Information
Number: 365/206
Name: Static information storage and retrieval > Read/write circuit > Noise suppression
Description: Subject matter having circuits for the cancellation or reduction of noise or spurious signals.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7447104 |
Word line driver for DRAM embedded in a logic process |
Nov. 4, 2008 |
| 7426150 |
Sense amplifier overdriving circuit and semiconductor device using the same |
Sep. 16, 2008 |
| 7426148 |
Method and apparatus for identifying short circuits in an integrated circuit device |
Sep. 16, 2008 |
| 7400541 |
Circuits and methods for data bus inversion in a semiconductor memory |
Jul. 15, 2008 |
| 7400544 |
Actively driven V.sub.REF for input buffer noise immunity |
Jul. 15, 2008 |
| 7391666 |
DRAM power bus control |
Jun. 24, 2008 |
| 7385864 |
SRAM static noise margin test structure suitable for on chip parametric measurements |
Jun. 10, 2008 |
| 7366006 |
SRAM with read assist |
Apr. 29, 2008 |
| 7362636 |
Semiconductor memory device |
Apr. 22, 2008 |
| 7349232 |
6F.sup.2 DRAM cell design with 3F-pitch folded digitline sense amplifier |
Mar. 25, 2008 |
| 7349266 |
Memory device with a data hold latch |
Mar. 25, 2008 |
| 7332780 |
Inverter, semiconductor logic circuit, static random access memory and data latch circuit |
Feb. 19, 2008 |
| 7324396 |
Sense amplifier organization for twin cell memory devices |
Jan. 29, 2008 |
| 7292499 |
Semiconductor device including duty cycle correction circuit |
Nov. 6, 2007 |
| 7292492 |
SRAM, semiconductor memory device, method for maintaining data in SRAM, and electronic device |
Nov. 6, 2007 |
| 7283382 |
Minimization of signal loss due to self-erase of imprinted data |
Oct. 16, 2007 |
| 7280412 |
Circuits and methods for data bus inversion in a semiconductor memory |
Oct. 9, 2007 |
| 7281094 |
Balanced bitcell for a multi-port register file |
Oct. 9, 2007 |
| 7277341 |
Semiconductor memory device |
Oct. 2, 2007 |
| 7277352 |
DRAM power bus control |
Oct. 2, 2007 |
| 7274613 |
Dynamic random access memory (DRAM) capable of canceling out complementary noise development in plate electrodes of memory cell capacitors |
Sep. 25, 2007 |
| 7274588 |
Compact and highly efficient DRAM cell |
Sep. 25, 2007 |
| 7254075 |
Integrated circuit memory system having dynamic memory bank count and page size |
Aug. 7, 2007 |
| 7254068 |
Semiconductor memory device |
Aug. 7, 2007 |
| 7242630 |
Memory device with reduced leakage current |
Jul. 10, 2007 |
| 7242627 |
Semiconductor device |
Jul. 10, 2007 |
| 7233524 |
Sense amplifier circuit |
Jun. 19, 2007 |
| 7219263 |
Method and system for minimizing memory corruption |
May. 15, 2007 |
| 7203123 |
Integrated DRAM memory device |
Apr. 10, 2007 |
| 7193915 |
Semiconductor memory device |
Mar. 20, 2007 |
| 7184346 |
Memory cell sensing with low noise generation |
Feb. 27, 2007 |
| 7173547 |
Offset compensation in local-probe data storage devices |
Feb. 6, 2007 |
| 7170776 |
Non-volatile memory device conducting comparison operation |
Jan. 30, 2007 |
| 7142021 |
Data inversion circuits having a bypass mode of operation and methods of operating the same |
Nov. 28, 2006 |
| 7133322 |
Probe storage device |
Nov. 7, 2006 |
| 7126868 |
Semiconductor device |
Oct. 24, 2006 |
| 7123047 |
Dynamic on-die termination management |
Oct. 17, 2006 |
| 7110319 |
Memory devices having reduced coupling noise between wordlines |
Sep. 19, 2006 |
| 7107467 |
Semiconductor memory device having a circuit for removing noise from a power line of the memory device using a plurality of decoupling capactors |
Sep. 12, 2006 |
| 7099204 |
Current sensing circuit with a current-compensated drain voltage regulation |
Aug. 29, 2006 |
| 7092292 |
Noise reduction technique for transistors and small devices utilizing an episodic agitation |
Aug. 15, 2006 |
| 7092274 |
Ferroelectric memory device |
Aug. 15, 2006 |
| 7079434 |
Noise suppression in memory device sensing |
Jul. 18, 2006 |
| 7068551 |
Semiconductor memory device |
Jun. 27, 2006 |
| 7068548 |
Semiconductor integrated circuit with noise reduction circuit |
Jun. 27, 2006 |
| 7050345 |
Memory device and method with improved power and noise characteristics |
May. 23, 2006 |
| 7027333 |
High reliability triple redundant memory element with integrated testability and voting structures on each latch |
Apr. 11, 2006 |
| 7023756 |
DRAM power bus control |
Apr. 4, 2006 |
| 7009870 |
Semiconductor integrated circuit apparatus |
Mar. 7, 2006 |
| 7002872 |
Semiconductor memory device with a decoupling capacitor |
Feb. 21, 2006 |
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