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Class Information
Number: 365/193
Name: Static information storage and retrieval > Read/write circuit > Signals > Strobe
Description: Subject matter where the particular signal is used for strobing the memory device.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7613049 |
Method and system for a serial peripheral interface |
Nov. 3, 2009 |
| 7606089 |
Data strobe signal generator for generating data strobe signal based on adjustable preamble value and semiconductor memory device with the same |
Oct. 20, 2009 |
| 7599244 |
Semiconductor memory, memory controller and control method for semiconductor memory |
Oct. 6, 2009 |
| 7599245 |
Output controller capable of generating only necessary control signals based on an activated selection signal |
Oct. 6, 2009 |
| 7593286 |
Write latency tracking using a delay lock loop in a synchronous DRAM |
Sep. 22, 2009 |
| 7593283 |
Semiconductor memory device |
Sep. 22, 2009 |
| 7593273 |
Read-leveling implementations for DDR3 applications on an FPGA |
Sep. 22, 2009 |
| 7590008 |
PVT compensated auto-calibration scheme for DDR3 |
Sep. 15, 2009 |
| 7590013 |
Semiconductor memory devices having variable additive latency |
Sep. 15, 2009 |
| 7590014 |
Semiconductor memory device with mirror function module and using the same |
Sep. 15, 2009 |
| 7590025 |
Systems and methods for clean DQS signal generation in source-synchronous DDR2 interface design |
Sep. 15, 2009 |
| 7586955 |
Interface circuit and semiconductor device |
Sep. 8, 2009 |
| 7586799 |
Devices, systems, and methods for independent output drive strengths |
Sep. 8, 2009 |
| 7580294 |
Semiconductor memory device comprising two rows of pads |
Aug. 25, 2009 |
| 7580301 |
Method control circuit performing adjustable data delay operation based upon phase difference between data strobe signal and clock signal, and associated method |
Aug. 25, 2009 |
| 7577046 |
Circuit and method for generating column path control signals in semiconductor device |
Aug. 18, 2009 |
| 7577048 |
Memory interface |
Aug. 18, 2009 |
| 7577014 |
Semiconductor memory device |
Aug. 18, 2009 |
| 7573760 |
Integrated circuit for sampling a sequence of data packets at a data output |
Aug. 11, 2009 |
| 7573759 |
Method for detecting data strobe signal |
Aug. 11, 2009 |
| 7564739 |
Storage cell design evaluation circuit including a wordline timing and cell access detection circuit |
Jul. 21, 2009 |
| 7561477 |
Data strobe synchronization circuit and method for double data rate, multi-bit writes |
Jul. 14, 2009 |
| 7558147 |
Semiconductor memory device |
Jul. 7, 2009 |
| 7558133 |
System and method for capturing data signals using a data strobe signal |
Jul. 7, 2009 |
| 7558132 |
Implementing calibration of DQS sampling during synchronous DRAM reads |
Jul. 7, 2009 |
| 7558151 |
Methods and circuits for DDR-2 memory device read data resynchronization |
Jul. 7, 2009 |
| 7554866 |
Circuit and method of controlling input/output sense amplifier of a semiconductor memory device |
Jun. 30, 2009 |
| 7554864 |
Semiconductor memory device including a global input/output line of a data transfer path and its surrounding circuits |
Jun. 30, 2009 |
| 7548470 |
Memory control method and memory control circuit |
Jun. 16, 2009 |
| 7542358 |
DLL with reduced size and semiconductor memory device including DLL and locking operation method of the same |
Jun. 2, 2009 |
| 7542371 |
Memory controller and memory system |
Jun. 2, 2009 |
| 7525855 |
Method of high-performance flash memory data transfer |
Apr. 28, 2009 |
| 7522459 |
Data input circuit of semiconductor memory device |
Apr. 21, 2009 |
| 7518947 |
Self-timed memory having common timing control circuit and method therefor |
Apr. 14, 2009 |
| 7518935 |
Synchronous RAM memory circuit |
Apr. 14, 2009 |
| 7515504 |
Phase controlled high speed interfaces |
Apr. 7, 2009 |
| 7512018 |
Column address enable signal generation circuit for semiconductor memory device |
Mar. 31, 2009 |
| 7508722 |
Memory device having strobe terminals with multiple functions |
Mar. 24, 2009 |
| 7508723 |
Buffered memory device |
Mar. 24, 2009 |
| 7504855 |
Multiple data rate memory interface architecture |
Mar. 17, 2009 |
| 7505336 |
Method and apparatus for synchronization of row and column access operations |
Mar. 17, 2009 |
| 7499371 |
Semiconductor memory system with a variable and settable preamble f |
Mar. 3, 2009 |
| 7499370 |
Synchronous semiconductor memory device |
Mar. 3, 2009 |
| 7499367 |
Semiconductor memory device having stacked bank structure |
Mar. 3, 2009 |
| 7489568 |
Delay stage-interweaved analog DLL/PLL |
Feb. 10, 2009 |
| 7486575 |
Semiconductor memories with block-dedicated programmable latency register |
Feb. 3, 2009 |
| 7480197 |
Implementing calibration of DQS sampling during synchronous DRAM reads |
Jan. 20, 2009 |
| 7471578 |
Internal voltage generation control circuit and internal voltage generation circuit using the same |
Dec. 30, 2008 |
| 7463534 |
Write apparatus for DDR SDRAM semiconductor memory device |
Dec. 9, 2008 |
| 7460417 |
Semiconductor device, semiconductor memory device and data strobe method |
Dec. 2, 2008 |
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