 |
|
 |
| |
 |
|
Class Information
Number: 365/189.12
Name: Static information storage and retrieval > Read/write circuit > With shift register
Description: Subject matter including a circuit which sequentially shifts the data information signal between one element and another in a memory array in a serial manner.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7619438 |
Methods of enabling the use of a defective programmable device |
Nov. 17, 2009 |
| 7606083 |
Semiconductor memory device with a noise filter and method of controlling the same |
Oct. 20, 2009 |
| 7606089 |
Data strobe signal generator for generating data strobe signal based on adjustable preamble value and semiconductor memory device with the same |
Oct. 20, 2009 |
| 7589988 |
Fast analog sampler for continuous recording and read-out and digital conversion system |
Sep. 15, 2009 |
| 7590027 |
Nonvolatile semiconductor memory device |
Sep. 15, 2009 |
| 7586797 |
Data output circuit of synchronous memory device |
Sep. 8, 2009 |
| 7573758 |
Phase-change random access memory (PRAM) performing program loop operation and method of programming the same |
Aug. 11, 2009 |
| 7570534 |
Enqueue event first-in, first-out buffer (FIFO) |
Aug. 4, 2009 |
| 7567471 |
High speed fanned out system architecture and input/output circuits for non-volatile memory |
Jul. 28, 2009 |
| 7561481 |
Memory controllers and pad sequence control methods thereof |
Jul. 14, 2009 |
| 7554877 |
Apparatus and method for data outputting |
Jun. 30, 2009 |
| 7551481 |
User configurable commands for flash memory |
Jun. 23, 2009 |
| 7551495 |
Semiconductor memory device with a data output circuit configured to output stored data during a first type of read operation and configured to output at least one data pattern during a second |
Jun. 23, 2009 |
| 7551501 |
Semiconductor memory device with temperature sensing device and operation thereof |
Jun. 23, 2009 |
| 7535772 |
Configurable data path architecture and clocking scheme |
May. 19, 2009 |
| 7535749 |
Dynamic memory word line driver scheme |
May. 19, 2009 |
| 7529135 |
Apparatus for controlling bitline bias voltage |
May. 5, 2009 |
| 7529145 |
Method for reading electrically programmable and erasable memory cells, with bit line precharge-ahead |
May. 5, 2009 |
| 7525833 |
Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers |
Apr. 28, 2009 |
| 7523232 |
Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system |
Apr. 21, 2009 |
| 7512021 |
Register configuration control device, register configuration control method, and program for implementing the method |
Mar. 31, 2009 |
| 7489567 |
FIFO memory device with non-volatile storage stage |
Feb. 10, 2009 |
| 7489565 |
Flash memory device including multi-buffer block |
Feb. 10, 2009 |
| 7489568 |
Delay stage-interweaved analog DLL/PLL |
Feb. 10, 2009 |
| 7486558 |
Non-volatile memory with managed execution of cached data |
Feb. 3, 2009 |
| 7483327 |
Apparatus and method for adjusting an operating parameter of an integrated circuit |
Jan. 27, 2009 |
| 7477553 |
Control device for controlling a buffer memory |
Jan. 13, 2009 |
| 7477564 |
Method and apparatus for redundant memory configuration in voltage island |
Jan. 13, 2009 |
| 7474571 |
Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage |
Jan. 6, 2009 |
| 7471576 |
Method of transferring data in an electrically programmable memory |
Dec. 30, 2008 |
| 7463521 |
Method for non-volatile memory with managed execution of cached data |
Dec. 9, 2008 |
| 7457172 |
Memory device and method having data path with multiple prefetch I/O configurations |
Nov. 25, 2008 |
| 7457189 |
Integrated circuit memory devices that support selective mode register set commands and related methods |
Nov. 25, 2008 |
| 7457169 |
Flash with consistent latency for read operations |
Nov. 25, 2008 |
| 7440349 |
Integrated semiconductor memory with determination of a chip temperature |
Oct. 21, 2008 |
| 7441072 |
Multilevel storage nonvolatile semiconductor memory device enabling high-speed data reading and high-speed data writing |
Oct. 21, 2008 |
| 7430142 |
Skew adjusting circuit and semiconductor integrated circuit |
Sep. 30, 2008 |
| 7428474 |
Integrated circuit with self-proofreading function and measuring device using the same |
Sep. 23, 2008 |
| 7428183 |
Synchronous semiconductor memory device for reducing power consumption |
Sep. 23, 2008 |
| 7428178 |
Memory circuit containing a chain of stages |
Sep. 23, 2008 |
| 7423927 |
Wave pipelined output circuit of synchronous memory device |
Sep. 9, 2008 |
| 7408808 |
User configurable commands for flash memory |
Aug. 5, 2008 |
| 7408815 |
SRAM cell controlled by flash memory cell |
Aug. 5, 2008 |
| 7403437 |
ROM test method and ROM test circuit |
Jul. 22, 2008 |
| 7403438 |
Memory array architecture and method for high-speed distribution measurements |
Jul. 22, 2008 |
| 7403446 |
Single late-write for standard synchronous SRAMs |
Jul. 22, 2008 |
| 7392417 |
Device for exchanging data signals between two clock domains |
Jun. 24, 2008 |
| 7385860 |
Data output circuit of synchronous memory device |
Jun. 10, 2008 |
| 7376024 |
User configurable commands for flash memory |
May. 20, 2008 |
| 7366031 |
Memory arrangement and method for addressing a memory |
Apr. 29, 2008 |
|
|
|
 |
|
 |
|
| |
Randomly Featured Patents |
|
