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Class Information
Number: 365/189.03
Name: Static information storage and retrieval > Read/write circuit > Plural use of terminal
Description: Subject matter which has a terminal connecting the memory to a data handling circuit and another diverse circuit.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7417888 |
Method and apparatus for resetable memory and design approach for same |
Aug. 26, 2008 |
| 7417901 |
Memory device having terminals for transferring multiple types of data |
Aug. 26, 2008 |
| 7405980 |
Shared terminal memory interface |
Jul. 29, 2008 |
| 7403437 |
ROM test method and ROM test circuit |
Jul. 22, 2008 |
| 7400539 |
Memory device having terminals for transferring multiple types of data |
Jul. 15, 2008 |
| 7366032 |
Multi-ported register cell with randomly accessible history |
Apr. 29, 2008 |
| 7362622 |
System for determining a reference level and evaluating a signal on the basis of the reference level |
Apr. 22, 2008 |
| 7353357 |
Apparatus and method for pipelined memory operations |
Apr. 1, 2008 |
| 7353356 |
High speed, low current consumption FIFO circuit |
Apr. 1, 2008 |
| 7345943 |
Unclocked eFUSE circuit |
Mar. 18, 2008 |
| 7339838 |
Method and apparatus for supplementary command bus |
Mar. 4, 2008 |
| 7335957 |
Semiconductor memory integrated circuit and layout method of the same |
Feb. 26, 2008 |
| 7336554 |
Semiconductor memory device having a reduced number of pins |
Feb. 26, 2008 |
| 7330951 |
Apparatus and method for pipelined memory operations |
Feb. 12, 2008 |
| 7315476 |
System and method for communicating information to a memory device using a reconfigured device pin |
Jan. 1, 2008 |
| 7310258 |
Memory chip architecture with high speed operation |
Dec. 18, 2007 |
| 7310276 |
Memory device and method having data path with multiple prefetch I/O configurations |
Dec. 18, 2007 |
| 7301835 |
Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability |
Nov. 27, 2007 |
| 7292480 |
Memory card having buffer memory for storing testing instruction |
Nov. 6, 2007 |
| 7292484 |
Sense amplifier with multiple bits sharing a common reference |
Nov. 6, 2007 |
| 7289372 |
Dual-port memory array using shared write drivers and read sense amplifiers |
Oct. 30, 2007 |
| 7287119 |
Integrated circuit memory device with delayed write command processing |
Oct. 23, 2007 |
| 7281094 |
Balanced bitcell for a multi-port register file |
Oct. 9, 2007 |
| 7274604 |
Memory device having terminals for transferring multiple types of data |
Sep. 25, 2007 |
| 7251168 |
Interface for access to non-volatile memory on an integrated circuit |
Jul. 31, 2007 |
| 7230857 |
Methods of modifying operational characteristic of memory devices using control bits received through data pins and related devices and systems |
Jun. 12, 2007 |
| 7215579 |
System and method for mode register control of data bus operating mode and impedance |
May. 8, 2007 |
| 7203100 |
Efficient implementation of a read scheme for multi-threaded register file |
Apr. 10, 2007 |
| 7200063 |
Circuitry for a programmable element |
Apr. 3, 2007 |
| 7187617 |
Memory system and method for strobing data, command and address signals |
Mar. 6, 2007 |
| 7184322 |
Semiconductor memory device and control method thereof |
Feb. 27, 2007 |
| 7184338 |
Semiconductor device, semiconductor device testing method, and programming method |
Feb. 27, 2007 |
| 7170773 |
Nonvolatile ferroelectric memory device having a multi-bit control function |
Jan. 30, 2007 |
| 7170815 |
Memory apparatus having multi-port architecture for supporting multi processor |
Jan. 30, 2007 |
| 7161845 |
Static random access memory device having a memory cell with multiple bit-elements |
Jan. 9, 2007 |
| 7161826 |
Low-noise leakage-tolerant register file technique |
Jan. 9, 2007 |
| 7158422 |
System and method for communicating information to a memory device using a reconfigured device pin |
Jan. 2, 2007 |
| 7151707 |
Memory device and method having data path with multiple prefetch I/O configurations |
Dec. 19, 2006 |
| 7136310 |
Programmable output driver turn-on time for an integrated circuit memory device |
Nov. 14, 2006 |
| 7123536 |
Voltage generation control circuit in semiconductor memory device, circuit using the same and method thereof |
Oct. 17, 2006 |
| 7116600 |
Memory device having terminals for transferring multiple types of data |
Oct. 3, 2006 |
| 7110321 |
Multi-bank integrated circuit memory devices having high-speed memory access timing |
Sep. 19, 2006 |
| 7110304 |
Dual port memory array using shared write drivers and read sense amplifiers |
Sep. 19, 2006 |
| 7102912 |
Integrated semiconductor memory device and method for operating an integrated semiconductor memory device |
Sep. 5, 2006 |
| 7079427 |
System and method for a high-speed access architecture for semiconductor memory |
Jul. 18, 2006 |
| 7073035 |
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules |
Jul. 4, 2006 |
| 7057941 |
Three-state memory cell |
Jun. 6, 2006 |
| 7042775 |
Semiconductor memory with wordline timing |
May. 9, 2006 |
| 7042773 |
Integrated circuit for storing operating parameters |
May. 9, 2006 |
| 7042792 |
Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays |
May. 9, 2006 |
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