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Class Information
Number: 365/185.31
Name: Static information storage and retrieval > Floating gate > Particular biasing > Erase > Nonsubstrate discharge
Description: Subject matter under 185.29 wherein the floating gate is erased by overlying electrodes or other means not directly connected to the substrate, and the charge carriers are not directly removed to the substrate.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7542351 |
Integrated circuit featuring a non-volatile memory with charge/discharge ramp rate control and method therefor |
Jun. 2, 2009 |
| 7508703 |
Non-volatile memory with boost structures |
Mar. 24, 2009 |
| 7508710 |
Operating non-volatile memory with boost structures |
Mar. 24, 2009 |
| 7307280 |
Memory devices with active and passive doped sol-gel layers |
Dec. 11, 2007 |
| 7259996 |
Flash memory |
Aug. 21, 2007 |
| 7239555 |
Erasing method for non-volatile memory |
Jul. 3, 2007 |
| 7203098 |
Methods of erasing flash memory |
Apr. 10, 2007 |
| 7120063 |
Flash memory cell and methods for programming and erasing |
Oct. 10, 2006 |
| 7099195 |
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices |
Aug. 29, 2006 |
| 7057932 |
Flash memory |
Jun. 6, 2006 |
| 7046557 |
Flash memory |
May. 16, 2006 |
| 6917069 |
Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor |
Jul. 12, 2005 |
| 6667910 |
Method and apparatus for discharging an array well in a flash memory device |
Dec. 23, 2003 |
| 6654291 |
Electrically erasable programmable read-only memory and method of erasing select memory cells |
Nov. 25, 2003 |
| 6166961 |
Approach to provide high external voltage for flash memory erase |
Dec. 26, 2000 |
| 6088269 |
Compact page-erasable EEPROM non-volatile memory |
Jul. 11, 2000 |
| 6034893 |
Non-volatile memory cell having dual avalanche injection elements |
Mar. 7, 2000 |
| 6028789 |
Zero-power CMOS non-volatile memory cell having an avalanche injection element |
Feb. 22, 2000 |
| 5798547 |
Non-volatile semiconductor memory device having NAND structure cells |
Aug. 25, 1998 |
| 5787034 |
Nonvolatile semiconductor memory having a stress relaxing voltage applied to erase gate during data write |
Jul. 28, 1998 |
| 5736891 |
Discharge circuit in a semiconductor memory |
Apr. 7, 1998 |
| 5677872 |
Low voltage erase of a flash EEPROM system having a common erase electrode for two individual erasable sectors |
Oct. 14, 1997 |
| 5650964 |
Method of inhibiting degradation of ultra short channel charge-carrying devices during discharge |
Jul. 22, 1997 |
| 5636160 |
Nonvolatile semiconductor memory having a stress relaxing voltage applied to erase gate during data write |
Jun. 3, 1997 |
| 5596531 |
Method for decreasing the discharge time of a flash EPROM cell |
Jan. 21, 1997 |
| 5544103 |
Compact page-erasable eeprom non-volatile memory |
Aug. 6, 1996 |
| 5544118 |
Flash EEPROM system cell array with defect management including an error correction scheme |
Aug. 6, 1996 |
| 5418742 |
Nonvolatile semiconductor memory with block erase select means |
May. 23, 1995 |
| 5380672 |
Dense vertical programmable read only memory cell structures and processes for making them |
Jan. 10, 1995 |
| 5369615 |
Method for optimum erasing of EEPROM |
Nov. 29, 1994 |
| 5313421 |
EEPROM with split gate source side injection |
May. 17, 1994 |
| 5303185 |
EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells |
Apr. 12, 1994 |
| 5291439 |
Semiconductor memory cell and memory array with inversion layer |
Mar. 1, 1994 |
| 5280446 |
Flash eprom memory circuit having source side programming |
Jan. 18, 1994 |
| 5267194 |
Electrically erasable programmable read-only-memory cell with side-wall floating gate |
Nov. 30, 1993 |
| 5216269 |
Electrically-programmable semiconductor memories with buried injector region |
Jun. 1, 1993 |
| 5208772 |
Gate EEPROM cell |
May. 4, 1993 |
| 5138576 |
Method and apparatus for erasing an array of electrically erasable EPROM cells |
Aug. 11, 1992 |
| 5103273 |
Nonvolatile memory array having cells with two tunnelling windows |
Apr. 7, 1992 |
| 5099297 |
EEPROM cell structure and architecture with programming and erase terminals shared between several cells |
Mar. 24, 1992 |
| 5095344 |
Highly compact EPROM and flash EEPROM devices |
Mar. 10, 1992 |
| 5091882 |
Nonvolatile semiconductor memory device and method of operating the same |
Feb. 25, 1992 |
| 5084745 |
Semiconductor memory device having a floating gate |
Jan. 28, 1992 |
| 5081057 |
Electrically alterable, nonvolatile, floating gate type memory device with reduced tunnelling area and fabrication thereof |
Jan. 14, 1992 |
| 5067108 |
Single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate |
Nov. 19, 1991 |
| 5053841 |
Nonvolatile semiconductor memory |
Oct. 1, 1991 |
| 5047814 |
E.sup.2 PROM cell including isolated control diffusion |
Sep. 10, 1991 |
| 5029130 |
Single transistor non-valatile electrically alterable semiconductor memory device |
Jul. 2, 1991 |
| 4998220 |
EEPROM with improved erase structure |
Mar. 5, 1991 |
| 4996572 |
Semiconductor memory device |
Feb. 26, 1991 |
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