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Class Information
Number: 365/185.18
Name: Static information storage and retrieval > Floating gate > Particular biasing
Description: Subject matter under 185.01 wherein an operating environment provides electrical settings to the floating gate device.
Sub-classes under this class:
| Class Number |
Class Name |
Patents |
| 365/185.23 |
Drive circuitry (e.g., word line driver) |
1,059 |
| 365/185.29 |
Erase |
1,677 |
| 365/185.26 |
Floating electrode (e.g., source, control gate, drain) |
680 |
| 365/185.25 |
Line charging (e.g., precharge, discharge, refresh) |
672 |
| 365/185.19 |
Multiple pulses (e.g., ramp) |
619 |
| 365/185.2 |
Reference signal (e.g., dummy cell) |
846 |
| 365/185.27 |
Substrate bias |
504 |
| 365/185.24 |
Threshold setting (e.g., conditioning) |
998 |
| 365/185.28 |
Tunnel programming |
1,084 |
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7619933 |
Reducing effects of program disturb in a memory device |
Nov. 17, 2009 |
| 7619929 |
Bias circuits and method for enhanced reliability of flash memory device |
Nov. 17, 2009 |
| 7619928 |
Semiconductor memory device including floating body memory cells and method of operating the same |
Nov. 17, 2009 |
| 7616507 |
Microprocessor boot-up controller, nonvolatile memory controller, and information processing system |
Nov. 10, 2009 |
| 7616493 |
Non-volatile semiconductor memory device |
Nov. 10, 2009 |
| 7616492 |
Evaluation circuit and evaluation method for the assessment of memory cell states |
Nov. 10, 2009 |
| 7616490 |
Programming non-volatile memory with dual voltage select gate structure |
Nov. 10, 2009 |
| 7616489 |
Memory array segmentation and methods |
Nov. 10, 2009 |
| 7616482 |
Multi-state memory cell with asymmetric charge trapping |
Nov. 10, 2009 |
| 7616479 |
Data writing method for flash memories |
Nov. 10, 2009 |
| 7613068 |
Read operation for non-volatile storage with compensation for coupling |
Nov. 3, 2009 |
| 7613053 |
Memory device and method of operating such a memory device |
Nov. 3, 2009 |
| 7613052 |
Memory device and method of operating such a memory device |
Nov. 3, 2009 |
| 7613044 |
Method and apparatus for high voltage operation for a high performance semiconductor memory device |
Nov. 3, 2009 |
| 7613043 |
Shifting reference values to account for voltage sag |
Nov. 3, 2009 |
| 7613027 |
Semiconductor memory device with dual storage node and fabricating and operating methods thereof |
Nov. 3, 2009 |
| 7609559 |
Word line drivers having a low pass filter circuit in non-volatile memory device |
Oct. 27, 2009 |
| 7609554 |
High voltage switching circuit |
Oct. 27, 2009 |
| 7609548 |
Method of programming a multi level cell |
Oct. 27, 2009 |
| 7606100 |
Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells |
Oct. 20, 2009 |
| 7606080 |
Erase verifying method of NAND flash memory device |
Oct. 20, 2009 |
| 7606079 |
Reducing power consumption during read operations in non-volatile storage |
Oct. 20, 2009 |
| 7606078 |
Method for programming of memory cells, in particular of the flash type, and corresponding programming architecture |
Oct. 20, 2009 |
| 7606075 |
Read operation for NAND memory |
Oct. 20, 2009 |
| 7606072 |
Non-volatile storage with compensation for source voltage drop |
Oct. 20, 2009 |
| 7606071 |
Compensating source voltage drop in non-volatile storage |
Oct. 20, 2009 |
| 7606070 |
Systems for margined neighbor reading for non-volatile memory read operations including coupling compensation |
Oct. 20, 2009 |
| 7606069 |
Bit-symbol recognition method and structure for multiple-bit storage in non-volatile memories |
Oct. 20, 2009 |
| 7602651 |
Semiconductor integrated circuit device |
Oct. 13, 2009 |
| 7602649 |
Method of operating an integrated circuit for reading the logical state of a memory cell |
Oct. 13, 2009 |
| 7602647 |
System that compensates for coupling based on sensing a neighbor using coupling |
Oct. 13, 2009 |
| 7602646 |
Threshold evaluation of EPROM cells |
Oct. 13, 2009 |
| 7602643 |
Non-volatile memory devices capable of reading data during multi-sector erase operation, and data read methods thereof |
Oct. 13, 2009 |
| 7599247 |
Memory and method of writing data |
Oct. 6, 2009 |
| 7599236 |
In-circuit Vt distribution bit counter for non-volatile memory devices |
Oct. 6, 2009 |
| 7599223 |
Non-volatile memory with linear estimation of initial programming voltage |
Oct. 6, 2009 |
| 7596033 |
Nonvolatile semiconductor memory device |
Sep. 29, 2009 |
| 7596031 |
Faster programming of highest multi-level state for non-volatile memory |
Sep. 29, 2009 |
| 7596029 |
Flash memory device including unified oscillation circuit and method of operating the device |
Sep. 29, 2009 |
| 7596028 |
Variable program and program verification methods for a virtual ground memory in easing buried drain contacts |
Sep. 29, 2009 |
| 7596022 |
Method for programming a multi-level non-volatile memory device |
Sep. 29, 2009 |
| 7596020 |
Multi-level nonvolatile semiconductor memory device capable of discretely controlling a charge storage layer potential based upon accumulated electrons |
Sep. 29, 2009 |
| 7593264 |
Method and apparatus for programming nonvolatile memory |
Sep. 22, 2009 |
| 7593262 |
Memory structure and operating method thereof |
Sep. 22, 2009 |
| 7593261 |
EEPROM devices and methods of operating and fabricating the same |
Sep. 22, 2009 |
| 7593260 |
Semiconductor memory device for storing multivalued data |
Sep. 22, 2009 |
| 7593248 |
Method, apparatus and system providing a one-time programmable memory device |
Sep. 22, 2009 |
| 7590005 |
Program and erase methods with substrate transient hot carrier injections in a non-volatile memory |
Sep. 15, 2009 |
| 7590004 |
Nonvolatile semiconductor memory having a plurality of interconnect layers |
Sep. 15, 2009 |
| 7590002 |
Resistance sensing and compensation for non-volatile storage |
Sep. 15, 2009 |
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